Home
last modified time | relevance | path

Searched +full:0 +full:x8000000 (Results 1 – 25 of 453) sorted by relevance

12345678910>>...19

/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbnx2_fw.h17 .state_value_clear = 0xffffff,
24 .mips_view_base = 0x8000000,
33 .state_value_clear = 0xffffff,
40 .mips_view_base = 0x8000000,
49 .state_value_clear = 0xffffff,
56 .mips_view_base = 0x8000000,
65 .state_value_clear = 0xffffff,
72 .mips_view_base = 0x8000000,
81 .state_value_clear = 0xffffff,
88 .mips_view_base = 0x8000000,
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dflctl-nand.txt26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-polarberry-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
H A Dmpfs-m100pfs-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
H A Dmpfs-icicle-kit-fabric.dtsi10 reg = <0x0 0x40000000 0x0 0xF0>;
11 microchip,sync-update-mask = /bits/ 32 <0>;
19 reg = <0x0 0x40000200 0x0 0x100>;
21 #size-cells = <0>;
31 #address-cells = <0x3>;
32 #interrupt-cells = <0x1>;
33 #size-cells = <0x2>;
35 reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
37 bus-range = <0x0 0x7f>;
40 interrupt-map = <0 0 0 1 &pcie_intc 0>,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/openbmc/u-boot/include/configs/
H A Dti_armv7_omap.h16 * access CS0 at is 0x8000000.
20 #define CONFIG_SYS_NAND_BASE 0x8000000
H A Dxilinx_zynqmp.h19 #define GICD_BASE 0xF9010000
20 #define GICC_BASE 0xF9020000
23 # define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
26 #define CONFIG_SYS_MEMTEST_START 0
37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000)
64 #define CONFIG_SYS_LOAD_ADDR 0x8000000
67 #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
75 "system.dtb ram $fdt_addr $fdt_size\0" \
76 "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
77 "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
[all …]
H A Dti816x_evm.h15 #define CONFIG_ENV_SIZE 0x2000
20 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
21 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
25 "fatload mmc 0 ${loadaddr} uImage;" \
35 #define CONFIG_SYS_SDRAM_BASE 0x80000000
41 #define CONFIG_SYS_TIMERBASE 0x4802E000
50 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
58 * access CS0 at is 0x8000000.
60 #define CONFIG_SYS_NAND_BASE 0x8000000
86 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35-pdk.dts15 reg = <0x80000000 0x8000000>,
16 <0x90000000 0x8000000>;
22 pinctrl-0 = <&pinctrl_esdhc1>;
30 MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
31 MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
32 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
33 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
34 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
35 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
41 MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
[all …]
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A Devb_rv1108.c28 GPIO2D2_GPIO = 0, in mach_cpu_init()
33 GPIO2D1_GPIO = 0, in mach_cpu_init()
47 return 0; in mach_cpu_init()
53 return 0; in board_init()
58 gd->ram_size = 0x8000000; in dram_init()
60 return 0; in dram_init()
65 gd->bd->bi_dram[0].start = 0x60000000; in dram_init_banksize()
66 gd->bd->bi_dram[0].size = 0x8000000; in dram_init_banksize()
68 return 0; in dram_init_banksize()
/openbmc/u-boot/board/elgin/elgin_rv1108/
H A Delgin_rv1108.c29 GPIO2D2_GPIO = 0, in mach_cpu_init()
34 GPIO2D1_GPIO = 0, in mach_cpu_init()
48 return 0; in mach_cpu_init()
56 gpio_direction_output(MODEM_ENABLE_GPIO, 0); in board_init()
58 return 0; in board_init()
63 gd->ram_size = 0x8000000; in dram_init()
65 return 0; in dram_init()
70 gd->bd->bi_dram[0].start = 0x60000000; in dram_init_banksize()
71 gd->bd->bi_dram[0].size = 0x8000000; in dram_init_banksize()
73 return 0; in dram_init_banksize()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dcpu.h11 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
12 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
13 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
14 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
16 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
17 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
18 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
20 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
21 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
22 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds3c6410-smdk6410.dts24 reg = <0x50000000 0x8000000>;
31 fin_pll: oscillator-0 {
35 #clock-cells = <0>;
42 #clock-cells = <0>;
49 reg = <0x18000000 0x8000000>;
54 reg = <0x18000000 0x10000>;
70 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
77 pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
83 pinctrl-0 = <&uart1_data>;
89 pinctrl-0 = <&uart2_data>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drcar-pci-ep.yaml79 reg = <0xfe000000 0x80000>,
80 <0xfe100000 0x100000>,
81 <0xfe200000 0x200000>,
82 <0x30000000 0x8000000>,
83 <0x38000000 0x8000000>;
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_devdis.h12 { "pbl", 0x0, 0x80000000 }, /* PBL */
13 { "esdhc", 0x0, 0x20000000 }, /* eSDHC */
14 { "qdma", 0x0, 0x800000 }, /* qDMA */
15 { "edma", 0x0, 0x400000 }, /* eDMA */
16 { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/
17 { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */
18 { "sata", 0x0, 0x8000 }, /* SATA */
19 { "sec", 0x0, 0x200 }, /* SEC */
20 { "dcu", 0x0, 0x2 }, /* Display controller Unit */
21 { "qe", 0x0, 0x1 }, /* QUICC Engine */
[all …]
/openbmc/linux/arch/mips/boot/dts/lantiq/
H A Ddanube.dtsi8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
44 reg = <0x101000 0x1000>;
49 reg = <0x102000 0x1000>;
54 reg = <0x103000 0x1000>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx31.h60 #define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
61 #define FSL_IMX31_SECURE_ROM_SIZE 0x4000
62 #define FSL_IMX31_ROM_ADDR 0x00404000
63 #define FSL_IMX31_ROM_SIZE 0x4000
64 #define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
65 #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
66 #define FSL_IMX31_IRAM_ADDR 0x1FFFC000
67 #define FSL_IMX31_IRAM_SIZE 0x4000
68 #define FSL_IMX31_I2C1_ADDR 0x43F80000
69 #define FSL_IMX31_I2C1_SIZE 0x4000
[all …]
/openbmc/u-boot/test/lib/
H A Dlmb.c20 ut_asserteq(lmb->memory.region[0].base, ram_base); in check_lmb()
21 ut_asserteq(lmb->memory.region[0].size, ram_size); in check_lmb()
25 if (num_reserved > 0) { in check_lmb()
26 ut_asserteq(lmb->reserved.region[0].base, base1); in check_lmb()
27 ut_asserteq(lmb->reserved.region[0].size, size1); in check_lmb()
37 return 0; in check_lmb()
56 const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000; in test_multi_alloc()
63 ut_assert(ram_end == 0 || ram_end > ram); in test_multi_alloc()
73 ut_asserteq(ret, 0); in test_multi_alloc()
77 ut_asserteq(ret, 0); in test_multi_alloc()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dvexpress-v2f-1xv7-ca53x2.dts20 arm,hbi = <0x247>;
21 arm,vexpress,site = <0xf>;
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0 0>;
54 reg = <0 1>;
67 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
75 /* Chipselect 2 is physically at 0x18000000 */
79 reg = <0 0x18000000 0 0x00800000>;
87 #address-cells = <0>;
[all …]

12345678910>>...19