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/openbmc/u-boot/arch/mips/dts/
H A Dci20.dts23 reg = <0x0 0x10000000
24 0x30000000 0x30000000>;
53 reg = <1 0 0x1000000>;
56 #size-cells = <0>;
79 partition@0 {
81 reg = <0x0 0x0 0x0 0x800000>;
84 partition@0x800000 {
86 reg = <0x0 0x800000 0x0 0x200000>;
89 partition@0xa00000 {
91 reg = <0x0 0xa00000 0x0 0x200000>;
[all …]
/openbmc/linux/drivers/virt/nitro_enclaves/
H A Dne_misc_dev_test.c6 #define INVALID_VALUE (~0ull)
17 * Add the region from 0x1000 to (0x1000 + 0x200000 - 1):
22 * num = 0
25 {0x1000, 0x200000, -EINVAL, 0, INVALID_VALUE, INVALID_VALUE},
28 * Add the region from 0x200000 to (0x200000 + 0x1000 - 1):
33 * num = 0
36 {0x200000, 0x1000, -EINVAL, 0, INVALID_VALUE, INVALID_VALUE},
39 * Add the region from 0x200000 to (0x200000 + 0x200000 - 1):
46 * {start=0x200000, end=0x3fffff}, // len=0x200000
49 {0x200000, 0x200000, 0, 1, 0x200000, 0x200000},
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-398-db.dts23 reg = <0x00000000 0x80000000>; /* 2 GB */
27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
32 pinctrl-0 = <&i2c0_pins>;
39 pinctrl-0 = <&uart0_pins>;
45 pinctrl-0 = <&uart1_pins>;
62 pcie@1,0 {
66 pcie@2,0 {
70 pcie@3,0 {
79 pinctrl-0 = <&spi1_pins>;
[all …]
H A Darmada-390-db.dts24 reg = <0x00000000 0x80000000>; /* 2 GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
38 reg = <0x50>;
62 pcie@1,0 {
67 pcie@2,0 {
72 pcie@3,0 {
81 pinctrl-0 = <&spi1_pins>;
84 flash@0 {
89 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-375-db.dts24 memory@0 {
26 reg = <0x00000000 0x40000000>; /* 1 GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
57 pinctrl-0 = <&spi0_pins>;
67 flash@0 {
[all …]
H A Darmada-388-db.dts25 reg = <0x00000000 0x10000000>; /* 256 MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
40 #sound-dai-cells = <0>;
42 reg = <0x4a>;
73 bm,pool-long = <0>;
78 phy0: ethernet-phy@0 {
[all …]
H A Darmada-370-db.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
33 memory@0 {
35 reg = <0x00000000 0x40000000>; /* 1 GB */
39 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
40 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
41 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
53 pinctrl-0 = <&ge0_rgmii_pins>;
60 pinctrl-0 = <&ge1_rgmii_pins>;
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dvecemu.c25 0x800000,
26 0x8b95c2,
27 0x9837f0,
28 0xa5fed7,
29 0xb504f3,
30 0xc5672a,
31 0xd744fd,
32 0xeac0c7
45 exp = ((s >> 23) & 0xff) - 127; in eexp2()
48 if (exp == 128 && (s & 0x7fffff) != 0) in eexp2()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_cyclone5_socdk-u-boot.dtsi42 label = "Flash 0 Raw Data";
43 reg = <0x0 0x800000>;
48 label = "Flash 0 jffs2 Filesystem";
49 reg = <0x800000 0x7800000>;
H A Darmada-375-db.dts70 reg = <0x00000000 0x40000000>; /* 1 GB */
74 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
75 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
76 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
77 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
81 pinctrl-0 = <&spi0_pins>;
91 spi-flash@0 {
96 reg = <0>; /* Chip select 0 */
104 pinctrl-0 = <&i2c0_pins>;
111 pinctrl-0 = <&i2c1_pins>;
[all …]
/openbmc/u-boot/include/configs/
H A Diconnect.h42 #define CONFIG_ENV_SECT_SIZE 0x20000
44 #define CONFIG_ENV_SIZE 0x20000
45 #define CONFIG_ENV_OFFSET 0x80000
54 "ubifsload 0x800000 ${kernel}; " \
55 "bootm 0x800000"
58 "console=console=ttyS0,115200\0" \
59 "mtdids=nand0=orion_nand\0" \
61 "kernel=/boot/uImage\0" \
62 "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
68 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
H A Dib62x0.h37 #define CONFIG_ENV_SECT_SIZE 0x20000
39 #define CONFIG_ENV_SIZE 0x20000
40 #define CONFIG_ENV_OFFSET 0xe0000
49 "ubifsload 0x800000 ${kernel}; " \
50 "ubifsload 0x700000 ${fdt}; " \
52 "fdt addr 0x700000; fdt resize; fdt chosen; " \
53 "bootz 0x800000 - 0x700000"
56 "console=console=ttyS0,115200\0" \
57 "mtdids=nand0=orion_nand\0" \
59 "kernel=/boot/zImage\0" \
[all …]
H A Ddockstar.h31 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
37 #define CONFIG_ENV_SIZE 0x20000 /* 128k */
38 #define CONFIG_ENV_ADDR 0x80000
39 #define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
48 "ubifsload 0x800000 ${kernel}; " \
49 "ubifsload 0x1100000 ${initrd}; " \
50 "bootm 0x800000 0x1100000"
53 "console=console=ttyS0,115200\0" \
54 "mtdids=nand0=orion_nand\0" \
56 "kernel=/boot/uImage\0" \
[all …]
H A Dnsa310s.h31 #define CONFIG_ENV_SECT_SIZE 0x20000
33 #define CONFIG_ENV_SIZE 0x20000
34 #define CONFIG_ENV_OFFSET 0xe0000
41 "ubifsload 0x800000 ${kernel}; " \
42 "ubifsload 0x700000 ${fdt}; " \
44 "fdt addr 0x700000; fdt resize; fdt chosen; " \
45 "bootz 0x800000 - 0x700000"
48 "console=console=ttyS0,115200\0" \
49 "mtdids=nand0=orion_nand\0" \
51 "kernel=/boot/zImage\0" \
[all …]
H A Dguruplug.h32 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
38 #define CONFIG_ENV_SIZE 0x20000 /* 128k */
39 #define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
53 "ubifsload 0x800000 ${kernel}; " \
54 "ubifsload 0x700000 ${fdt}; " \
56 "fdt addr 0x700000; fdt resize; fdt chosen; " \
57 "bootz 0x800000 - 0x700000"
60 "console=console=ttyS0,115200\0" \
61 "mtdids=nand0=orion_nand\0" \
63 "kernel=/boot/zImage\0" \
[all …]
H A Dls1088aqds.h18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-agn-hw.h12 #define IWLAGN_RTC_INST_LOWER_BOUND (0x000000)
13 #define IWLAGN_RTC_INST_UPPER_BOUND (0x020000)
15 #define IWLAGN_RTC_DATA_LOWER_BOUND (0x800000)
16 #define IWLAGN_RTC_DATA_UPPER_BOUND (0x80C000)
23 #define IWL60_RTC_INST_LOWER_BOUND (0x000000)
24 #define IWL60_RTC_INST_UPPER_BOUND (0x040000)
25 #define IWL60_RTC_DATA_LOWER_BOUND (0x800000)
26 #define IWL60_RTC_DATA_UPPER_BOUND (0x814000)
42 #define IWLAGN_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm: 1 milliwatt */
50 #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */
/openbmc/u-boot/post/lib_powerpc/
H A Dthreex.c40 0x1234,
41 0x5678,
42 0x1234 | 0x5678
46 0x1234,
47 0x5678,
48 0x1234 | ~0x5678
52 0x1234,
53 0x5678,
54 0x1234 ^ 0x5678
58 0x1234,
[all …]
/openbmc/u-boot/drivers/dma/
H A Dfsl_dma.c17 #define FSL_DMA_MAX_SIZE (0x3ffffff)
64 volatile fsl_dma_t *dma = &dma_base->dma[0]; in dma_check()
76 if (status != 0) in dma_check()
84 volatile fsl_dma_t *dma = &dma_base->dma[0]; in dma_init()
88 out_dma32(&dma->sr, 0xffffffff); /* clear any errors */ in dma_init()
94 volatile fsl_dma_t *dma = &dma_base->dma[0]; in dmacpy()
100 out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); in dmacpy()
101 out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); in dmacpy()
128 return 0; in dmacpy()
140 uint *p = 0; in dma_meminit()
[all …]
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm750-evb.dts51 reg = <0x0 0x20000000>;
71 flash@0 {
76 reg = <0>;
82 bbuboot1@0 {
84 reg = <0x0000000 0x80000>;
89 reg = <0x0080000 0x80000>;
94 reg = <0x0100000 0x40000>;
99 reg = <0x0140000 0xC0000>;
103 reg = <0x0200000 0x400000>;
107 reg = <0x0600000 0x700000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D21423 seq=$(basename "$0")
32 trap "_cleanup; exit \$status" 0 1 2 3 15
44 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file
52 # 0x800000 and 0x800008, their original values are 0x4008000000a00000
53 # and 0x4008000000a00802 (5 sectors for compressed data each).
55 $QEMU_IO -c "write -c -P 0x11 0 2M" -c "write -c -P 0x11 2M 2M" "$TEST_IMG" \
59 poke_file "$TEST_IMG" $((0x800000)) "\x40\x06"
60 $QEMU_IO -c "read -P 0x11 0 4M" "$TEST_IMG" 2>&1 | _filter_qemu_io | _filter_testdir
69 # addresses [0xa00000, 0xdfffff]), but the decompression algorithm
72 poke_file "$TEST_IMG" $((0x800000)) "\x7f\xfe"
[all …]

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