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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c36 #define TOPOLOGY_TEST_OK 0
46 /* 0 1 2 3 */
49 { 1, 1, 0, 0 }, /* USB3H */
50 { 1, 1, 1, 0 }, /* USB3D */
52 { 1, 0, 0, 0 }, /* QSGMII */
53 { 4, 0, 0, 0 }, /* XAUI */
54 { 2, 0, 0, 0 } /* RXAUI */
61 u8 serdes_unit_count[MAX_UNITS_ID] = { 0 };
65 /* 0 1 2 3 4 5 6 */
66 { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dpasemi_nand.c25 #define LBICTRL_LPCCTL_NR 0x00004000
39 while (len > 0x800) { in pasemi_read_buf()
40 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
41 buf += 0x800; in pasemi_read_buf()
42 len -= 0x800; in pasemi_read_buf()
50 while (len > 0x800) { in pasemi_write_buf()
51 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
52 buf += 0x800; in pasemi_write_buf()
53 len -= 0x800; in pasemi_write_buf()
89 return 0; in pasemi_attach_chip()
[all …]
H A Dcs553x_nand.c11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
29 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
30 #define CAP_CS5535 0x2df000ULL
31 #define CAP_CS5536 0x5df500ULL
34 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
35 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
36 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
39 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
40 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
19 memory@0 {
21 reg = <0x00000000 0x00000000 0x00000000 0x10000000>;
26 #clock-cells = <0>;
33 #size-cells = <0x00>;
34 #address-cells = <0x01>;
70 isa = <0>;
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dga100.c46 nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0x00000003); in ga100_chan_stop()
54 const int gfid = 0; in ga100_chan_start()
56 nvkm_wr32(device, runl->chan + (chan->id * 4), 0x00000002); in ga100_chan_start()
57 nvkm_wr32(device, runl->addr + 0x0090, (gfid << 16) | chan->id); /* INTERNAL_DOORBELL. */ in ga100_chan_start()
65 nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0xffffffff); in ga100_chan_unbind()
74 nvkm_wo32(chan->inst, 0x010, 0x0000face); in ga100_chan_ramfc_write()
75 nvkm_wo32(chan->inst, 0x030, 0x7ffff902); in ga100_chan_ramfc_write()
76 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in ga100_chan_ramfc_write()
77 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); in ga100_chan_ramfc_write()
78 nvkm_wo32(chan->inst, 0x084, 0x20400000); in ga100_chan_ramfc_write()
[all …]
/openbmc/qemu/tests/tcg/s390x/
H A Dsam.S2 #define DAT_PSWM 0x400c00180000000
3 #define VIRTUAL_BASE 0x123456789abcd000
5 .org 0x8e
7 .org 0x150
9 .org 0x1d0 /* program new PSW */
10 .quad 0,pgm_handler
11 .org 0x200 /* lowcore padding */
37 .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
39 .quad 0x2000000000000,0 /* disabled wait */
41 /* DT = 0b11 (region-first-table), TL = 3 (2k entries) */
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
12 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
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/openbmc/linux/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/openbmc/linux/arch/riscv/kernel/
H A Dmodule.c38 return 0; in apply_r_riscv_32_rela()
44 return 0; in apply_r_riscv_64_rela()
51 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
52 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
53 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
54 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
56 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
57 return 0; in apply_r_riscv_branch_rela()
64 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
65 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-decoder.yaml151 reg = <0x16020000 0x1000>, /*VDEC_MISC*/
152 <0x16021000 0x800>, /*VDEC_LD*/
153 <0x16021800 0x800>, /*VDEC_TOP*/
154 <0x16022000 0x1000>, /*VDEC_CM*/
155 <0x16023000 0x1000>, /*VDEC_AD*/
156 <0x16024000 0x1000>, /*VDEC_AV*/
157 <0x16025000 0x1000>, /*VDEC_PP*/
158 <0x16026800 0x800>, /*VP8_VD*/
159 <0x16027000 0x800>, /*VP6_VD*/
160 <0x16027800 0x800>, /*VP8_VL*/
[all …]
/openbmc/u-boot/board/freescale/mx6sabreauto/
H A DREADME60 # load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
64 # load mmc 0:1 ${loadaddr} uImage
68 # mmc write ${loadaddr} 0x1000 0x4000
78 - Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
80 # mmc write 18000000 0x800 0x800
/openbmc/linux/Documentation/devicetree/bindings/hsi/
H A Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/openbmc/u-boot/board/freescale/mx6sabresd/
H A DREADME48 => mmc partconf 2 1 0 0
52 => ums 0 mmc 2
99 # mmc write ${loadaddr} 0x1000 0x4000
109 - Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
111 # mmc write 18000000 0x800 0x800
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c15 #define LYNX_28G_PCC8 0x10a0
16 #define LYNX_28G_PCC8_SGMII 0x1
17 #define LYNX_28G_PCC8_SGMII_DIS 0x0
19 #define LYNX_28G_PCCC 0x10b0
20 #define LYNX_28G_PCCC_10GBASER 0x9
21 #define LYNX_28G_PCCC_USXGMII 0x1
22 #define LYNX_28G_PCCC_SXGMII_DIS 0x0
27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
33 #define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf119.c40 const u32 hoff = 0x800 * head; in gf119_sor_hda_device_entry()
42 nvkm_mask(device, 0x616548 + hoff, 0x00000070, head << 4); in gf119_sor_hda_device_entry()
49 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_eld()
52 for (i = 0; i < size; i++) in gf119_sor_hda_eld()
53 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | data[i]); in gf119_sor_hda_eld()
54 for (; i < 0x60; i++) in gf119_sor_hda_eld()
55 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_sor_hda_eld()
56 nvkm_mask(device, 0x10ec10 + soff, 0x80000002, 0x80000002); in gf119_sor_hda_eld()
63 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_hpd()
64 u32 data = 0x80000000; in gf119_sor_hda_hpd()
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dls2080aqds.h20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #define SPD_EEPROM_ADDRESS1 0x51
33 #define SPD_EEPROM_ADDRESS2 0x52
34 #define SPD_EEPROM_ADDRESS3 0x53
35 #define SPD_EEPROM_ADDRESS4 0x54
36 #define SPD_EEPROM_ADDRESS5 0x55
37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dlitex,liteeth.yaml56 minimum: 0x800
57 default: 0x800
78 reg = <0x8021000 0x100>,
79 <0x8020800 0x100>,
80 <0x8030000 0x2000>;
84 litex,slot-size = <0x800>;
85 interrupts = <0x11 0x1>;
90 #size-cells = <0>;
92 eth_phy: ethernet-phy@0 {
93 reg = <0>;
/openbmc/linux/arch/m68k/mac/
H A Dmacboing.c23 static __u8 mac_asc_wave_tab[ 0x800 ];
26 * Alan's original sine table; needs interpolating to 0x800
27 * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
30 0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
31 0, -39, -75, -103, -121, -127, -121, -103, -75, -39
37 static volatile __u8* mac_asc_regs = ( void* )0x50F14000;
44 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
74 * mac_asc_regs[ 0x800 ] & 0xF0 != 0 in mac_init_asc()
84 mac_asc_regs = ( void* )0x50010000; in mac_init_asc()
147 for ( i = 0; i < 0x400; i++ ) in mac_init_asc()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
H A Dgk20a.c29 nvkm_mask(device, 0x137250, 0x3f, 0); in gk20a_privring_init_privring_ring()
31 nvkm_mask(device, 0x000200, 0x20, 0); in gk20a_privring_init_privring_ring()
33 nvkm_mask(device, 0x000200, 0x20, 0x20); in gk20a_privring_init_privring_ring()
35 nvkm_wr32(device, 0x12004c, 0x4); in gk20a_privring_init_privring_ring()
36 nvkm_wr32(device, 0x122204, 0x2); in gk20a_privring_init_privring_ring()
37 nvkm_rd32(device, 0x122204); in gk20a_privring_init_privring_ring()
43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_privring_init_privring_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_privring_init_privring_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_privring_init_privring_ring()
52 u32 status0 = nvkm_rd32(device, 0x120058); in gk20a_privring_intr()
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
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