Searched +full:0 +full:x7fef000 (Results 1 – 5 of 5) sorted by relevance
66 const: 0x104c70 - 0xb00d71 - 0xb00f72 - 0xb01073 - 0xb013129 reg = <0x00 0x02900000 0x00 0x1000>,130 <0x00 0x02907000 0x00 0x400>,131 <0x00 0x0d000000 0x00 0x00800000>,132 <0x00 0x10000000 0x00 0x00001000>;134 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;[all …]
15 #clock-cells = <0>;17 clock-frequency = <0>;21 #clock-cells = <0>;23 clock-frequency = <0>;30 reg = <0x0 0x70000000 0x0 0x800000>;33 ranges = <0x0 0x0 0x70000000 0x800000>;35 atf-sram@0 {36 reg = <0x0 0x20000>;42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */45 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]
10 #clock-cells = <0>;18 reg = <0x00 0x70000000 0x00 0x100000>;21 ranges = <0x00 0x00 0x70000000 0x100000>;23 atf-sram@0 {24 reg = <0x00 0x20000>;30 reg = <0x00 0x00100000 0x00 0x1c000>;33 ranges = <0x00 0x00 0x00100000 0x1c000>;38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */45 reg = <0x4044 0x10>;[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x00 0x70000000 0x00 0x200000>;25 ranges = <0x0 0x00 0x70000000 0x200000>;28 reg = <0x1c0000 0x20000>;32 reg = <0x1e0000 0x1c000>;36 reg = <0x1fc000 0x4000>;42 reg = <0x0 0x43000000 0x0 0x20000>;45 ranges = <0x0 0x0 0x43000000 0x20000>;49 reg = <0x00000014 0x4>;[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x0 0x70000000 0x0 0x400000>;25 ranges = <0x0 0x0 0x70000000 0x400000>;27 atf-sram@0 {28 reg = <0x0 0x20000>;32 reg = <0x1f0000 0x10000>;36 reg = <0x200000 0x200000>;42 reg = <0x00 0x00104000 0x00 0x18000>;45 ranges = <0x00 0x00 0x00104000 0x18000>;[all …]