/openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
H A D | setup-sh7786.c | 35 DEFINE_RES_MEM(0xffea0000, 0x100), 36 DEFINE_RES_IRQ(evt2irq(0x700)), 37 DEFINE_RES_IRQ(evt2irq(0x720)), 38 DEFINE_RES_IRQ(evt2irq(0x760)), 39 DEFINE_RES_IRQ(evt2irq(0x740)), 44 .id = 0, 62 DEFINE_RES_MEM(0xffeb0000, 0x100), 63 DEFINE_RES_IRQ(evt2irq(0x780)), 67 DEFINE_RES_MEM(0xffeb0000, 0x100), 69 DEFINE_RES_IRQ(0), [all …]
|
H A D | setup-shx3.c | 20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2 34 DEFINE_RES_MEM(0xffc30000, 0x100), 35 DEFINE_RES_IRQ(evt2irq(0x700)), 36 DEFINE_RES_IRQ(evt2irq(0x720)), 37 DEFINE_RES_IRQ(evt2irq(0x760)), 38 DEFINE_RES_IRQ(evt2irq(0x740)), 43 .id = 0, 57 DEFINE_RES_MEM(0xffc40000, 0x100), 58 DEFINE_RES_IRQ(evt2irq(0x780)), 59 DEFINE_RES_IRQ(evt2irq(0x7a0)), [all …]
|
H A D | setup-sh7780.c | 25 DEFINE_RES_MEM(0xffe00000, 0x100), 26 DEFINE_RES_IRQ(evt2irq(0x700)), 31 .id = 0, 46 DEFINE_RES_MEM(0xffe10000, 0x100), 47 DEFINE_RES_IRQ(evt2irq(0xb80)), 65 DEFINE_RES_MEM(0xffd80000, 0x30), 66 DEFINE_RES_IRQ(evt2irq(0x580)), 67 DEFINE_RES_IRQ(evt2irq(0x5a0)), 68 DEFINE_RES_IRQ(evt2irq(0x5c0)), 73 .id = 0, [all …]
|
H A D | setup-sh7722.c | 30 .addr = 0xffe0000c, 32 .mid_rid = 0x21, 35 .addr = 0xffe00014, 37 .mid_rid = 0x22, 40 .addr = 0xffe1000c, 42 .mid_rid = 0x25, 45 .addr = 0xffe10014, 47 .mid_rid = 0x26, 50 .addr = 0xffe2000c, 52 .mid_rid = 0x29, [all …]
|
H A D | setup-sh7343.c | 24 DEFINE_RES_MEM(0xffe00000, 0x100), 25 DEFINE_RES_IRQ(evt2irq(0xc00)), 30 .id = 0, 44 DEFINE_RES_MEM(0xffe10000, 0x100), 45 DEFINE_RES_IRQ(evt2irq(0xc20)), 64 DEFINE_RES_MEM(0xffe20000, 0x100), 65 DEFINE_RES_IRQ(evt2irq(0xc40)), 84 DEFINE_RES_MEM(0xffe30000, 0x100), 85 DEFINE_RES_IRQ(evt2irq(0xc60)), 99 [0] = { [all …]
|
H A D | setup-sh7763.c | 26 DEFINE_RES_MEM(0xffe00000, 0x100), 27 DEFINE_RES_IRQ(evt2irq(0x700)), 32 .id = 0, 47 DEFINE_RES_MEM(0xffe08000, 0x100), 48 DEFINE_RES_IRQ(evt2irq(0xb80)), 68 DEFINE_RES_MEM(0xffe10000, 0x100), 69 DEFINE_RES_IRQ(evt2irq(0xf00)), 83 [0] = { 84 .start = 0xffe80000, 85 .end = 0xffe80000 + 0x58 - 1, [all …]
|
H A D | setup-sh7770.c | 22 DEFINE_RES_MEM(0xff923000, 0x100), 23 DEFINE_RES_IRQ(evt2irq(0x9a0)), 28 .id = 0, 42 DEFINE_RES_MEM(0xff924000, 0x100), 43 DEFINE_RES_IRQ(evt2irq(0x9c0)), 62 DEFINE_RES_MEM(0xff925000, 0x100), 63 DEFINE_RES_IRQ(evt2irq(0x9e0)), 82 DEFINE_RES_MEM(0xff926000, 0x100), 83 DEFINE_RES_IRQ(evt2irq(0xa00)), 102 DEFINE_RES_MEM(0xff927000, 0x100), [all …]
|
H A D | setup-sh7734.c | 32 DEFINE_RES_MEM(0xffe40000, 0x100), 33 DEFINE_RES_IRQ(evt2irq(0x8c0)), 38 .id = 0, 53 DEFINE_RES_MEM(0xffe41000, 0x100), 54 DEFINE_RES_IRQ(evt2irq(0x8e0)), 74 DEFINE_RES_MEM(0xffe42000, 0x100), 75 DEFINE_RES_IRQ(evt2irq(0x900)), 95 DEFINE_RES_MEM(0xffe43000, 0x100), 96 DEFINE_RES_IRQ(evt2irq(0x920)), 116 DEFINE_RES_MEM(0xffe44000, 0x100), [all …]
|
H A D | setup-sh7723.c | 30 DEFINE_RES_MEM(0xffe00000, 0x100), 31 DEFINE_RES_IRQ(evt2irq(0xc00)), 36 .id = 0, 51 DEFINE_RES_MEM(0xffe10000, 0x100), 52 DEFINE_RES_IRQ(evt2irq(0xc20)), 72 DEFINE_RES_MEM(0xffe20000, 0x100), 73 DEFINE_RES_IRQ(evt2irq(0xc40)), 92 DEFINE_RES_MEM(0xa4e30000, 0x100), 93 DEFINE_RES_IRQ(evt2irq(0x900)), 112 DEFINE_RES_MEM(0xa4e40000, 0x100), [all …]
|
H A D | setup-sh7785.c | 27 DEFINE_RES_MEM(0xffea0000, 0x100), 28 DEFINE_RES_IRQ(evt2irq(0x700)), 33 .id = 0, 48 DEFINE_RES_MEM(0xffeb0000, 0x100), 49 DEFINE_RES_IRQ(evt2irq(0x780)), 69 DEFINE_RES_MEM(0xffec0000, 0x100), 70 DEFINE_RES_IRQ(evt2irq(0x980)), 90 DEFINE_RES_MEM(0xffed0000, 0x100), 91 DEFINE_RES_IRQ(evt2irq(0x9a0)), 111 DEFINE_RES_MEM(0xffee0000, 0x100), [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
H A D | qcom,qfprom.yaml | 88 reg = <0 0x00784000 0 0x8ff>, 89 <0 0x00780000 0 0x7a0>, 90 <0 0x00782000 0 0x100>, 91 <0 0x00786000 0 0x1fff>; 100 reg = <0x25b 0x1>; 113 reg = <0 0x00784000 0 0x8ff>; 118 reg = <0x1eb 0x1>;
|
/openbmc/linux/drivers/video/fbdev/ |
H A D | sunxvr500.c | 58 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props() 59 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props() 68 return 0; in e3d_get_props() 72 * 0x04000000, the following video layout register values: 74 * RAMDAC_VID_WH 0x03ff04ff 75 * RAMDAC_VID_CFG 0x1a0b0088 76 * RAMDAC_VID_32FB_0 0x04000000 77 * RAMDAC_VID_32FB_1 0x04800000 78 * RAMDAC_VID_8FB_0 0x05000000 79 * RAMDAC_VID_8FB_1 0x05200000 [all …]
|
/openbmc/u-boot/arch/riscv/include/asm/ |
H A D | encoding.h | 16 #define MSTATUS_UIE 0x00000001 17 #define MSTATUS_SIE 0x00000002 18 #define MSTATUS_HIE 0x00000004 19 #define MSTATUS_MIE 0x00000008 20 #define MSTATUS_UPIE 0x00000010 21 #define MSTATUS_SPIE 0x00000020 22 #define MSTATUS_HPIE 0x00000040 23 #define MSTATUS_MPIE 0x00000080 24 #define MSTATUS_SPP 0x00000100 25 #define MSTATUS_HPP 0x00000600 [all …]
|
/openbmc/linux/arch/sh/kernel/cpu/sh4/ |
H A D | setup-sh7760.c | 17 UNUSED = 0, 44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 49 INTC_VECT(DMAC, 0x6c0), 50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), [all …]
|
H A D | setup-sh7750.c | 19 [0] = { 20 .start = 0xffc80000, 21 .end = 0xffc80000 + 0x58 - 1, 26 .start = evt2irq(0x480), 43 DEFINE_RES_MEM(0xffe00000, 0x20), 44 DEFINE_RES_IRQ(evt2irq(0x4e0)), 49 .id = 0, 63 DEFINE_RES_MEM(0xffe80000, 0x100), 64 DEFINE_RES_IRQ(evt2irq(0x700)), 82 DEFINE_RES_MEM(0xffd80000, 0x30), [all …]
|
/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
|
H A D | imx53-pinfunc.h | 13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 [all …]
|
H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
|
/openbmc/linux/include/linux/mfd/mt6331/ |
H A D | registers.h | 10 #define MT6331_STRUP_CON0 0x0 11 #define MT6331_STRUP_CON2 0x2 12 #define MT6331_STRUP_CON3 0x4 13 #define MT6331_STRUP_CON4 0x6 14 #define MT6331_STRUP_CON5 0x8 15 #define MT6331_STRUP_CON6 0xA 16 #define MT6331_STRUP_CON7 0xC 17 #define MT6331_STRUP_CON8 0xE 18 #define MT6331_STRUP_CON9 0x10 19 #define MT6331_STRUP_CON10 0x12 [all …]
|
/openbmc/linux/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_reg.h | 12 #define ANALOGIX_DP_TX_SW_RESET 0x14 13 #define ANALOGIX_DP_FUNC_EN_1 0x18 14 #define ANALOGIX_DP_FUNC_EN_2 0x1C 15 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 16 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 17 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 19 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 20 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 22 #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8 24 #define ANALOGIX_DP_PLL_REG_1 0xfc [all …]
|
/openbmc/u-boot/arch/arm/dts/ |
H A D | imx53-pinfunc.h | 13 #define IMX_PAD_SION 0x40000000 18 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 19 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 20 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 21 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 22 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 23 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 24 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 25 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 26 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 [all …]
|
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_7_0_d.h | 27 #define mmMC_CONFIG 0x800 28 #define mmMC_ARB_AGE_CNTL 0x9bf 29 #define mmMC_ARB_RET_CREDITS2 0x9c0 30 #define mmMC_ARB_FED_CNTL 0x9c1 31 #define mmMC_ARB_GECC2_STATUS 0x9c2 32 #define mmMC_ARB_GECC2_MISC 0x9c3 33 #define mmMC_ARB_GECC2_DEBUG 0x9c4 34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5 35 #define mmMC_ARB_GECC2 0x9c9 36 #define mmMC_ARB_GECC2_CLI 0x9ca [all …]
|
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/ |
H A D | iomux-mx51.h | 47 MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 48 MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), 49 MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 50 MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 51 MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 52 MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 53 MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), 54 MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 55 MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL), 56 MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL), [all …]
|
/openbmc/linux/arch/arm/mach-imx/ |
H A D | pm-imx6.c | 31 #define CCR 0x0 32 #define BM_CCR_WB_COUNT (0x7 << 16) 33 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) 34 #define BM_CCR_RBC_EN (0x1 << 27) 36 #define CLPCR 0x54 37 #define BP_CLPCR_LPM 0 38 #define BM_CLPCR_LPM (0x3 << 0) 39 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) 40 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 41 #define BM_CLPCR_SBYOS (0x1 << 6) [all …]
|
/openbmc/u-boot/board/freescale/imx8mq_evk/ |
H A D | lpddr4_timing_b0.c | 16 { DDRC_DBG1(0), 0x00000001 }, 18 { DDRC_PWRCTL(0), 0x00000001 }, 19 { DDRC_MSTR(0), 0xa3080020 }, 20 { DDRC_MSTR2(0), 0x00000000 }, 21 { DDRC_RFSHTMG(0), 0x006100E0 }, 22 { DDRC_INIT0(0), 0xC003061B }, 23 { DDRC_INIT1(0), 0x009D0000 }, 24 { DDRC_INIT3(0), 0x00D4002D }, 26 { DDRC_INIT4(0), 0x00330008 }, 28 { DDRC_INIT4(0), 0x00310008 }, [all …]
|