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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dtegra.h10 #define NV_PA_ARM_PERIPHBASE 0x50040000
11 #define NV_PA_PG_UP_BASE 0x60000000
12 #define NV_PA_TMRUS_BASE 0x60005010
13 #define NV_PA_CLK_RST_BASE 0x60006000
14 #define NV_PA_FLOW_BASE 0x60007000
15 #define NV_PA_GPIO_BASE 0x6000D000
16 #define NV_PA_EVP_BASE 0x6000F000
17 #define NV_PA_APB_MISC_BASE 0x70000000
18 #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
[all …]
/openbmc/linux/arch/arm/mach-tegra/
H A Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra124-soctherm.yaml88 minimum: 0
99 - 0
115 # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE)
116 - 0
130 property is missing. A value of 0 will interrupt on every OC
143 default: 0
148 default: 0
176 const: 0
240 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
241 <0x60006000 0x400>; /* CAR reg_base */
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/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]