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/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dtegra.h10 #define NV_PA_SDRAM_BASE 0x00000000
11 #define NV_PA_MC_BASE 0x7000F000
15 #define TEGRA_USB1_BASE 0xC5000000
/openbmc/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dtegra.h9 #define NV_PA_MC_BASE 0x7000F000
10 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
14 #define TEGRA_USB1_BASE 0x7D000000
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-mc.yaml48 const: 0
69 reg = <0x7000f000 0x400>, /* Controller registers */
70 <0x58000000 0x02000000>; /* GART aperture */
74 interrupts = <0 77 4>;
76 #iommu-cells = <0>;
H A Dnvidia,tegra30-mc.yaml64 "^emc-timings-[0-9]+$":
73 "^timing-[0-9]+$":
134 reg = <0x7000f000 0x400>;
138 interrupts = <0 77 4>;
151 0x0000000a /* MC_EMEM_ARB_CFG */
152 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
153 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
154 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
155 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
156 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/devfreq/
H A Dnvidia,tegra30-actmon.yaml90 reg = <0x7000f000 0x400>;
94 interrupts = <0 77 4>;
103 reg = <0x7000f400 0x400>;
104 interrupts = <0 78 4>;
111 #interconnect-cells = <0>;
116 reg = <0x6000c800 0x400>;
117 interrupts = <0 45 4>;
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20.dtsi14 reg = <0x50000000 0x00024000>;
24 ranges = <0x54000000 0x54000000 0x04000000>;
28 reg = <0x54040000 0x00040000>;
37 reg = <0x54080000 0x00040000>;
46 reg = <0x540c0000 0x00040000>;
55 reg = <0x54100000 0x00040000>;
64 reg = <0x54140000 0x00040000>;
73 reg = <0x54180000 0x00040000>;
81 reg = <0x54200000 0x00040000>;
89 nvidia,head = <0>;
[all …]
H A Dtegra30.dtsi16 reg = <0x00003000 0x00000800 /* PADS registers */
17 0x00003800 0x00000200 /* AFI registers */
18 0x10000000 0x10000000>; /* configuration space */
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28 bus-range = <0x00 0xff>;
32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
[all …]
/openbmc/linux/drivers/scsi/isci/
H A Dregisters.h66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000)
69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000)
72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800)
75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00)
78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF)
79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0)
81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT)
86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
[all …]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]