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Searched +full:0 +full:x70008000 (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/doc/device-tree-bindings/nand/
H A Dnvidia,tegra20-nand.txt42 nand-controller@0x70008000 {
45 #size-cells = <0>;
46 nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
49 nand@0 {
50 reg = <0>;
/openbmc/linux/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dnvidia-tegra20-nand.txt47 reg = <0x70008000 0x100>;
54 nand@0 {
55 reg = <0>;
62 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
/openbmc/u-boot/include/configs/
H A Dm53menlo.h23 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
28 #define CONFIG_SYS_MEMTEST_START 0x70000000
29 #define CONFIG_SYS_MEMTEST_END 0x8ff00000
58 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
90 #define CONFIG_FEC_MXC_PHYADDR 0x0
113 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
124 #define CONFIG_MXC_USB_FLAGS 0
132 #define CONFIG_DWC_AHSATA_PORT_ID 0
171 #define CONFIG_LOADADDR 0x70800000
179 #define CONFIG_SPL_TEXT_BASE 0x70008000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl-imx-esdhc.yaml113 default: 0
132 default: 0
142 default: 0
152 default: 0
192 reg = <0x70004000 0x4000>;
199 reg = <0x70008000 0x4000>;
201 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
202 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
/openbmc/linux/arch/m68k/include/asm/
H A Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51.dtsi46 reg = <0xe0000000 0x4000>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 #size-cells = <0>;
78 cpu: cpu@0 {
81 reg = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20.dtsi14 reg = <0x50000000 0x00024000>;
24 ranges = <0x54000000 0x54000000 0x04000000>;
28 reg = <0x54040000 0x00040000>;
37 reg = <0x54080000 0x00040000>;
46 reg = <0x540c0000 0x00040000>;
55 reg = <0x54100000 0x00040000>;
64 reg = <0x54140000 0x00040000>;
73 reg = <0x54180000 0x00040000>;
81 reg = <0x54200000 0x00040000>;
89 nvidia,head = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]