Searched +full:0 +full:x70000014 (Results 1 – 6 of 6) sorted by relevance
96 reg = <0x70000014 0x10>, /* Tri-state registers */97 <0x70000080 0x20>, /* Mux registers */98 <0x700000a0 0x14>, /* Pull-up/down registers */99 <0x70000868 0xa8>; /* Pad control registers */105 nvidia,pull = <0>;106 nvidia,tristate = <0>;
21 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */22 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */23 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */24 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */25 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */26 #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */27 #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */28 #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */29 #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */32 #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */[all …]
14 reg = <0x50000000 0x00024000>;24 ranges = <0x54000000 0x54000000 0x04000000>;28 reg = <0x54040000 0x00040000>;37 reg = <0x54080000 0x00040000>;46 reg = <0x540c0000 0x00040000>;55 reg = <0x54100000 0x00040000>;64 reg = <0x54140000 0x00040000>;73 reg = <0x54180000 0x00040000>;81 reg = <0x54200000 0x00040000>;89 nvidia,head = <0>;[all …]
17 memory@0 {19 reg = <0 0>;24 reg = <0x40000000 0x40000>;27 ranges = <0 0x40000000 0x40000>;30 reg = <0x400 0x3fc00>;37 reg = <0x50000000 0x00024000>;51 ranges = <0x54000000 0x54000000 0x04000000>;55 reg = <0x54040000 0x00040000>;67 reg = <0x54080000 0x00040000>;79 reg = <0x540c0000 0x00040000>;[all …]
22 #define PT_NULL 029 #define PT_LOOS 0x6000000030 #define PT_HIOS 0x6fffffff31 #define PT_LOPROC 0x7000000032 #define PT_HIPROC 0x7fffffff34 #define PT_GNU_STACK (PT_LOOS + 0x474e551)35 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)37 #define PT_MIPS_REGINFO 0x7000000038 #define PT_MIPS_RTPROC 0x7000000139 #define PT_MIPS_OPTIONS 0x70000002[all …]
82 #define OP_MASK_OP 0x3f84 #define OP_MASK_RS 0x1f86 #define OP_MASK_FR 0x1f88 #define OP_MASK_FMT 0x1f90 #define OP_MASK_BCC 0x792 #define OP_MASK_CODE 0x3ff94 #define OP_MASK_CODE2 0x3ff96 #define OP_MASK_RT 0x1f98 #define OP_MASK_FT 0x1f100 #define OP_MASK_CACHE 0x1f[all …]