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Searched +full:0 +full:x60080000 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dcalimain.h32 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
33 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
49 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
57 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
58 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
59 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
62 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
77 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
80 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
83 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
[all …]
H A Dedb93xx.h38 #define CONFIG_ENV_SECT_SIZE 0x00020000
42 #define CONFIG_ENV_SECT_SIZE 0x00020000
46 #define CONFIG_ENV_SECT_SIZE 0x00020000
50 #define CONFIG_ENV_SECT_SIZE 0x00040000
54 #define CONFIG_ENV_SECT_SIZE 0x00020000
58 #define CONFIG_ENV_SECT_SIZE 0x00040000
62 #define CONFIG_ENV_SECT_SIZE 0x00040000
66 #define CONFIG_ENV_SECT_SIZE 0x00020000
83 #define CONFIG_SYS_SERIAL0 0x808C0000
84 #define CONFIG_SYS_SERIAL1 0x808D0000
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsifive,fu740-pcie.yaml94 reg = <0xe 0x00000000 0x0 0x80000000>,
95 <0xd 0xf0000000 0x0 0x10000000>,
96 <0x0 0x100d0000 0x0 0x1000>;
100 bus-range = <0x0 0xff>;
101 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
102 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
103 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
104 … <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
105 num-lanes = <0x8>;
109 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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/openbmc/u-boot/configs/
H A Drock_defconfig5 CONFIG_SYS_TEXT_BASE=0x60000000
6 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DEBUG_UART_BASE=0x20064000
12 CONFIG_SPL_STACK_R_ADDR=0x60080000
19 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
31 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks as…
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
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/openbmc/qemu/hw/mips/
H A Djazz.c78 address_space_read(&address_space_memory, 0x90000071, in rtc_read()
86 uint8_t buf = val & 0xff; in rtc_write()
87 address_space_write(&address_space_memory, 0x90000071, in rtc_write()
104 return 0xff; in dma_dummy_read()
144 sysbus_mmio_map(sysbus, 0, 0x80001000); in mips_jazz_init_net()
145 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); in mips_jazz_init_net()
149 checksum = 0; in mips_jazz_init_net()
150 for (i = 0; i < 6; i++) { in mips_jazz_init_net()
153 if (checksum > 0xff) { in mips_jazz_init_net()
154 checksum = (checksum + 1) & 0xff; in mips_jazz_init_net()
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
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