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Searched +full:0 +full:x600000000 (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dmicrochip,sparx5.yaml52 0x600000000 in all the Sparx5 variants.
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
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/openbmc/linux/drivers/cpufreq/
H A Dintel_pstate.c355 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; in intel_pstate_set_itmt_prio()
360 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. in intel_pstate_set_itmt_prio()
363 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. in intel_pstate_set_itmt_prio()
473 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { in intel_pstate_init_acpi_perf_limits()
474 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", in intel_pstate_init_acpi_perf_limits()
600 cpu = all_cpu_data[0]; in update_turbo_state()
609 struct cpudata *cpu = all_cpu_data[0]; in min_perf_pct_min()
613 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; in min_perf_pct_min()
628 return (s16)(epb & 0x0f); in intel_pstate_get_epb()
637 * When hwp_req_data is 0, means that caller didn't read in intel_pstate_get_epp()
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