Searched +full:0 +full:x53fd4000 (Results 1 – 10 of 10) sorted by relevance
53 reg = <0x53fd4000 0x4000>;54 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,55 <0 72 IRQ_TYPE_LEVEL_HIGH>;
42 reg = <0x0fffc000 0x4000>;56 reg = <0x50000000 0x10000000>;63 reg = <0x50000000 0x40000>;68 reg = <0x50004000 0x4000>;80 reg = <0x50008000 0x4000>;93 reg = <0x53fa8000 0x4000>;98 reg = <0x53fa8000 0xc>;103 reg = <0x53fc0000 0x4000>;108 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;115 reg = <0x53fd4000 0x4000>;[all …]
16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */17 #define IRAM_SIZE 0x00020000 /* 128 KB */19 #define LOW_LEVEL_SRAM_STACK 0x1001E00024 #define AIPS1_BASE_ADDR 0x43F0000026 #define MAX_BASE_ADDR 0x43F0400027 #define EVTMON_BASE_ADDR 0x43F0800028 #define CLKCTL_BASE_ADDR 0x43F0C00029 #define I2C1_BASE_ADDR 0x43F8000030 #define I2C3_BASE_ADDR 0x43F8400031 #define ATA_BASE_ADDR 0x43F8C000[all …]
35 #size-cells = <0>;37 cpu@0 {40 reg = <0>;48 reg = <0x68000000 0x100000>;60 reg = <0x1fffc000 0x4000>;63 ranges = <0 0x1fffc000 0x4000>;70 reg = <0x43f00000 0x100000>;75 reg = <0x43f80000 0x4000>;79 #size-cells = <0>;85 reg = <0x43f84000 0x4000>;[all …]
39 #size-cells = <0>;41 cpu@0 {44 reg = <0>;52 reg = <0x68000000 0x10000000>;64 reg = <0x30000000 0x1000>;73 reg = <0x43f00000 0x100000>;78 #size-cells = <0>;80 reg = <0x43f80000 0x4000>;89 #size-cells = <0>;91 reg = <0x43f84000 0x4000>;[all …]
48 #size-cells = <0>;49 cpu@0 {52 reg = <0x0>;60 reg = <0x0fffc000 0x4000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;79 clock-frequency = <0>;84 #clock-cells = <0>;89 usbphy0: usbphy-0 {[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;60 reg = <0x68000000 0x8000000>;66 #clock-cells = <0>;82 reg = <0x43f00000 0x100000>;87 reg = <0x43f00000 0x4000>;92 #size-cells = <0>;94 reg = <0x43f80000 0x4000>;103 #size-cells = <0>;[all …]
51 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0>;84 reg = <0x0fffc000 0x4000>;90 #clock-cells = <0>;96 #clock-cells = <0>;102 #clock-cells = <0>;103 clock-frequency = <0>;108 #clock-cells = <0>;119 usbphy0: usbphy-0 {[all …]
26 #define MXC_CCM_CLPCR 0x5427 #define MXC_CCM_CLPCR_LPM_OFFSET 028 #define MXC_CCM_CLPCR_LPM_MASK 0x330 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)31 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)33 #define MXC_CORTEXA8_PLAT_LPC 0xc34 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)37 #define MXC_SRPG_NEON_SRPGCR 0x28038 #define MXC_SRPG_ARM_SRPGCR 0x2a039 #define MXC_SRPG_EMPGC0_SRPGCR 0x2c0[all …]
27 u32 cgr0; /* Clock Gating Control 0 */33 u32 dcvr0; /* DPTC Comparator Value 0 */37 u32 ltr0; /* Load Tracking 0 */41 u32 ltbr0; /* Load Tracking Buffer 0 */43 u32 pcmr0; /* Power Management Control 0 */47 u32 lpimr0; /* Low Power Interrupt Mask 0 */53 u32 ctl0; /* control 0 */54 u32 cfg0; /* configuration 0 */104 u32 res1[0x1f1];106 u32 fuse_regs[0x20];[all …]