Searched +full:0 +full:x53fb4000 (Results 1 – 8 of 8) sorted by relevance
84 reg = <0x53fb4000 0x4000>;
74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)75 * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved76 * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)77 * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved78 * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved79 * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved80 * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved81 * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX[all …]
16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */17 #define IRAM_SIZE 0x00020000 /* 128 KB */19 #define LOW_LEVEL_SRAM_STACK 0x1001E00024 #define AIPS1_BASE_ADDR 0x43F0000026 #define MAX_BASE_ADDR 0x43F0400027 #define EVTMON_BASE_ADDR 0x43F0800028 #define CLKCTL_BASE_ADDR 0x43F0C00029 #define I2C1_BASE_ADDR 0x43F8000030 #define I2C3_BASE_ADDR 0x43F8400031 #define ATA_BASE_ADDR 0x43F8C000[all …]
39 #size-cells = <0>;41 cpu@0 {44 reg = <0>;52 reg = <0x68000000 0x10000000>;64 reg = <0x30000000 0x1000>;73 reg = <0x43f00000 0x100000>;78 #size-cells = <0>;80 reg = <0x43f80000 0x4000>;89 #size-cells = <0>;91 reg = <0x43f84000 0x4000>;[all …]
48 #size-cells = <0>;49 cpu@0 {52 reg = <0x0>;60 reg = <0x0fffc000 0x4000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;79 clock-frequency = <0>;84 #clock-cells = <0>;89 usbphy0: usbphy-0 {[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;60 reg = <0x68000000 0x8000000>;66 #clock-cells = <0>;82 reg = <0x43f00000 0x100000>;87 reg = <0x43f00000 0x4000>;92 #size-cells = <0>;94 reg = <0x43f80000 0x4000>;103 #size-cells = <0>;[all …]
51 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0>;84 reg = <0x0fffc000 0x4000>;90 #clock-cells = <0>;96 #clock-cells = <0>;102 #clock-cells = <0>;103 clock-frequency = <0>;108 #clock-cells = <0>;119 usbphy0: usbphy-0 {[all …]
27 u32 cgr0; /* Clock Gating Control 0 */33 u32 dcvr0; /* DPTC Comparator Value 0 */37 u32 ltr0; /* Load Tracking 0 */41 u32 ltbr0; /* Load Tracking Buffer 0 */43 u32 pcmr0; /* Power Management Control 0 */47 u32 lpimr0; /* Low Power Interrupt Mask 0 */53 u32 ctl0; /* control 0 */54 u32 cfg0; /* configuration 0 */104 u32 res1[0x1f1];106 u32 fuse_regs[0x20];[all …]