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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
90 const: 0
113 "^pll[0|1]-refclk$":
126 const: 0
157 const: 0
166 "^serdes@[0-9a-f]+$":
210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
214 ranges = <0x5000000 0x5000000 0x10000>;
218 #clock-cells = <0>;
224 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/openbmc/u-boot/include/configs/
H A Devb_ast2400.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x43000000
H A Dncsi_ast2600a1.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Devb_ast2600a1.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Dslt_ast2600.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Dfpga_ast2600.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Dncsi_ast2600a0.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Devb_ast2600a0.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Devb_ast2600.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Devb_ast2500.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
H A Dfpga_ast2600_spl.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
21 #define CONFIG_SPL_TEXT_BASE 0x00000000
22 #define CONFIG_SPL_MAX_SIZE 0x0000E800
23 #define CONFIG_SPL_STACK 0x10010000
25 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
26 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
H A Devb_ast2500_spl.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x83000000
20 #define CONFIG_SPL_TEXT_BASE 0x00000000
21 #define CONFIG_SPL_MAX_SIZE 0x00010000
22 #define CONFIG_SPL_STACK 0x1e729000
24 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
H A Devb_ast2600a0_spl.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
29 #define CONFIG_SYS_MONITOR_LEN 0xe0000
32 #define CONFIG_SPL_TEXT_BASE 0x00000000
33 #define CONFIG_SPL_MAX_SIZE 0x0000E800
34 #define CONFIG_SPL_STACK 0x10010000
36 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
37 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
H A Devb_ast2600_spl.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
21 #define CONFIG_SPL_TEXT_BASE 0x00000000
22 #define CONFIG_SPL_MAX_SIZE 0x00010000
23 #define CONFIG_SPL_STACK 0x10016000
24 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
26 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x00010000
31 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
[all …]
H A Dintel_ast2600.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
21 #define CONFIG_SPL_TEXT_BASE 0x00000000
22 #define CONFIG_SPL_MAX_SIZE 0x00010000
23 #define CONFIG_SPL_STACK 0x10016000
24 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
26 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x00010000
34 "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \
[all …]
H A Devb_ast2600a1_spl.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
21 #define CONFIG_SPL_TEXT_BASE 0x00000000
22 #define CONFIG_SPL_MAX_SIZE 0x00010000
23 #define CONFIG_SPL_STACK 0x10016000
24 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
26 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x00010000
31 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
[all …]
H A Devb_ast2600_spl_emmc.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
21 #define CONFIG_SPL_TEXT_BASE 0x00000000
22 #define CONFIG_SPL_MAX_SIZE 0x00010000
23 #define CONFIG_SPL_STACK 0x10016000
24 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
30 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
31 "bootside=a\0" \
[all …]
/openbmc/u-boot/configs/
H A Dsmdkv310_defconfig3 CONFIG_SYS_TEXT_BASE=0x43E00000
24 CONFIG_SMC911X_BASE=0x5000000
H A Darndale_defconfig3 CONFIG_SYS_TEXT_BASE=0x43E00000
32 CONFIG_SMC911X_BASE=0x5000000
H A Dsmdk5420_defconfig3 CONFIG_SYS_TEXT_BASE=0x23E00000
34 CONFIG_SF_DEFAULT_MODE=0
39 CONFIG_SMC911X_BASE=0x5000000
H A Dodroid-xu3_defconfig3 CONFIG_SYS_TEXT_BASE=0x43E00000
40 CONFIG_SMC911X_BASE=0x5000000
55 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
56 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
H A Dsmdk5250_defconfig5 CONFIG_SYS_TEXT_BASE=0x43E00000
39 CONFIG_SF_DEFAULT_MODE=0
44 CONFIG_SMC911X_BASE=0x5000000
H A Dpeach-pi_defconfig3 CONFIG_SYS_TEXT_BASE=0x23E00000
44 CONFIG_SF_DEFAULT_MODE=0
49 CONFIG_SMC911X_BASE=0x5000000
H A Dpeach-pit_defconfig3 CONFIG_SYS_TEXT_BASE=0x23E00000
43 CONFIG_SF_DEFAULT_MODE=0
48 CONFIG_SMC911X_BASE=0x5000000

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