/openbmc/u-boot/arch/mips/lib/ |
H A D | stack.c | 10 gd->start_addr_sp -= 0x500; in arch_reserve_stacks() 11 gd->start_addr_sp &= ~0xFFF; in arch_reserve_stacks() 14 0x500, gd->start_addr_sp); in arch_reserve_stacks() 16 return 0; in arch_reserve_stacks()
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | lpc18xx-ccu.h | 13 #define CLK_APB3_BUS 0x100 14 #define CLK_APB3_I2C1 0x108 15 #define CLK_APB3_DAC 0x110 16 #define CLK_APB3_ADC0 0x118 17 #define CLK_APB3_ADC1 0x120 18 #define CLK_APB3_CAN0 0x128 19 #define CLK_APB1_BUS 0x200 20 #define CLK_APB1_MOTOCON_PWM 0x208 21 #define CLK_APB1_I2C0 0x210 22 #define CLK_APB1_I2S 0x218 [all …]
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/openbmc/linux/arch/alpha/kernel/ |
H A D | sys_takara.c | 41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw() 42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw() 43 outl(mask & 0xffff0000UL, regaddr); in takara_update_irq_hw() 77 * The PALcode will have passed us vectors 0x800 or 0x810, in takara_device_interrupt() 92 intstatus = inw(0x500) & 15; in takara_device_interrupt() 102 if (intstatus & 1) handle_irq(16+0); in takara_device_interrupt() 111 int irq = (vector - 0x800) >> 4; in takara_srm_device_interrupt() 125 unsigned int ctlreg = inl(0x500); in takara_init_irq() 128 ctlreg &= ~0x8000; in takara_init_irq() 129 outl(ctlreg, 0x500); in takara_init_irq() [all …]
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/openbmc/linux/arch/powerpc/boot/dts/fsl/ |
H A D | pq3-rmu-0.dtsi | 2 * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ] 39 reg = <0xd3000 0x500>; 40 ranges = <0x0 0xd3000 0x500>; 42 message-unit@0 { 44 reg = <0x0 0x100>; 46 53 2 0 0 /* msg1_tx_irq */ 47 54 2 0 0>;/* msg1_rx_irq */ 51 reg = <0x100 0x100>; 53 55 2 0 0 /* msg2_tx_irq */ 54 56 2 0 0>;/* msg2_rx_irq */ [all …]
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H A D | qoriq-rmu-0.dtsi | 2 * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ] 39 reg = <0xd3000 0x500>; 40 ranges = <0x0 0xd3000 0x500>; 42 message-unit@0 { 44 reg = <0x0 0x100>; 46 60 2 0 0 /* msg1_tx_irq */ 47 61 2 0 0>;/* msg1_rx_irq */ 51 reg = <0x100 0x100>; 53 62 2 0 0 /* msg2_tx_irq */ 54 63 2 0 0>;/* msg2_rx_irq */ [all …]
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/openbmc/linux/arch/powerpc/platforms/52xx/ |
H A D | mpc52xx_pm.c | 35 return 0; in mpc52xx_pm_valid() 51 tmp &= ~(0x3 << (pin * 2)); in mpc52xx_set_wakeup_gpio() 57 return 0; in mpc52xx_set_wakeup_gpio() 75 if (of_address_to_resource(np, 0, &res)) { in mpc52xx_pm_prepare() 81 mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */ in mpc52xx_pm_prepare() 89 sdram = mbar + 0x100; in mpc52xx_pm_prepare() 90 cdm = mbar + 0x200; in mpc52xx_pm_prepare() 91 intr = mbar + 0x500; in mpc52xx_pm_prepare() 92 gpiow = mbar + 0xc00; in mpc52xx_pm_prepare() 93 sram = mbar + 0x8000; /* Those will be handled by the */ in mpc52xx_pm_prepare() [all …]
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/openbmc/u-boot/board/freescale/mx7ulp_evk/ |
H A D | plugin.S | 9 ldr r2, =0x403f0000 10 ldr r3, =0x00000000 11 str r3, [r2, #0xdc] 13 ldr r2, =0x403e0000 14 ldr r3, =0x01000020 15 str r3, [r2, #0x40] 16 ldr r3, =0x01000000 17 str r3, [r2, #0x500] 18 ldr r3, =0x80808080 19 str r3, [r2, #0x50c] [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | msm8994.dtsi | 29 #clock-cells = <0>; 36 #clock-cells = <0>; 44 #size-cells = <0>; 46 CPU0: cpu@0 { 49 reg = <0x0 0x0>; 62 reg = <0x0 0x1>; 70 reg = <0x0 0x2>; 78 reg = <0x0 0x3>; 86 reg = <0x0 0x100>; 99 reg = <0x0 0x101>; [all …]
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/openbmc/linux/arch/s390/include/asm/ |
H A D | kvm_para.h | 16 * use 0x500 as KVM hypercall 28 #define HYPERCALL_FMT_1 , "0" (r2) 79 " diag 2,4,0x500\n" \ 93 GENERATE_KVM_HYPERCALL_FUNC(0) 110 return 0; in kvm_arch_para_features() 115 return 0; in kvm_arch_para_hints()
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/openbmc/linux/drivers/media/usb/stk1160/ |
H A D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000 17 #define STK1160_RMCTL 0x00c 20 #define STK1160_POSVA 0x010 21 #define STK1160_POSV_L 0x010 22 #define STK1160_POSV_M 0x011 23 #define STK1160_POSV_H 0x012 30 * with bit #7 (0x?? OR 0x80 to activate). 32 #define STK1160_DCTRL 0x100 39 * Bit 0 - Horizontal Decimation Control 40 * 0 Horizontal decimation is disabled. [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | armada-xp.dtsi | 70 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 76 reg = <0x1400 0x500>; 81 reg = <0x08000 0x1000>; 82 cache-id-part = <0x100>; 91 pinctrl-0 = <&spi0_pins>; 103 reg = <0x11000 0x100>; 108 reg = <0x11100 0x100>; 113 pinctrl-0 = <&uart2_pins>; 115 reg = <0x12200 0x100>; 119 clocks = <&coreclk 0>; [all …]
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/openbmc/u-boot/drivers/mmc/ |
H A D | gen_atmel_mci.c | 33 # define MCI_BUS 0 59 return readl(&mci->version) & 0x00000fff; in atmel_mci_get_version() 71 cmdr, cmdr & 0x3F, arg, status, msg); in dump_cmd() 78 blklen &= 0xfffc; in mci_set_blklen() 80 /* MCI IP version >= 0x200 has blkr */ in mci_set_blklen() 81 if (version >= 0x200) in mci_set_blklen() 107 u32 clkodd = 0; 112 if (hz > 0) { 113 if (version >= 0x500) { 125 for (clkdiv = 0; clkdiv < 255; clkdiv++) { [all …]
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/openbmc/linux/drivers/bus/ |
H A D | omap_l3_noc.h | 16 #define CUSTOM_ERROR 0x2 17 #define STANDARD_ERROR 0x0 18 #define INBAND_ERROR 0x0 19 #define L3_APPLICATION_ERROR 0x0 20 #define L3_DEBUG_ERROR 0x1 23 #define L3_TARG_STDERRLOG_MAIN 0x48 24 #define L3_TARG_STDERRLOG_HDR 0x4c 25 #define L3_TARG_STDERRLOG_MSTADDR 0x50 26 #define L3_TARG_STDERRLOG_INFO 0x58 27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | toshiba,tc358775.yaml | 28 description: i2c address of the bridge, 0x0f 48 port@0: 65 - port@0 88 reg = <0x078b8000 0x500>; 91 #size-cells = <0>; 95 reg = <0x0f>; 105 #size-cells = <0>; 107 port@0 { 108 reg = <0>; 125 reg = <0x1a98000 0x25c>; [all …]
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/openbmc/linux/arch/arm/boot/dts/marvell/ |
H A D | armada-xp.dtsi | 35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 41 reg = <0x1400 0x500>; 46 reg = <0x08000 0x1000>; 47 cache-id-part = <0x100>; 55 pinctrl-0 = <&uart2_pins>; 57 reg = <0x12200 0x100>; 61 clocks = <&coreclk 0>; 67 pinctrl-0 = <&uart3_pins>; 69 reg = <0x12300 0x100>; 73 clocks = <&coreclk 0>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | microchip,csi2dc.yaml | 76 port@0: 129 - port@0 147 reg = <0xe1404000 0x500>; 153 #size-cells = <0>; 154 port@0 { 155 reg = <0>; /* must be 0, first child port */ 177 reg = <0xe1404000 0x500>; 185 #size-cells = <0>; 186 port@0 { 187 reg = <0>; /* must be 0, first child port */
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/openbmc/u-boot/arch/arm/mach-stm32mp/include/mach/ |
H A D | sys_proto.h | 6 #define CPU_STMP32MP15x 0x500 11 #define CPU_REVA 0x1000 12 #define CPU_REVB 0x2000
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/openbmc/linux/drivers/net/ethernet/ibm/ehea/ |
H A D | ehea_hw.h | 37 u64 qpx_reserved1[(0x098 - 0x058) / 8]; 39 u64 qpx_reserved2[(0x100 - 0x0A0) / 8]; 43 u64 qpx_reserved3[(0x140 - 0x118) / 8]; 45 u64 qpx_reserved4[(0x170 - 0x148) / 8]; 47 u64 qpx_reserved5[(0x1B0 - 0x178) / 8]; 53 u64 qpx_reserved6[(0x220 - 0x1D8) / 8]; 55 u64 qpx_reserved7[(0x240 - 0x228) / 8]; 62 u64 qpx_reserved8[(0x300 - 0x270) / 8]; 78 u64 qpx_reserved9[(0x400 - 0x378) / 8]; 79 u64 reserved_ext[(0x500 - 0x400) / 8]; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | jcore,pit.txt | 22 reg = < 0x200 0x30 0x500 0x30 >; 23 interrupts = < 0x48 >;
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/openbmc/linux/include/soc/imx/ |
H A D | cpu.h | 15 #define MXC_CPU_IMX6SL 0x60 16 #define MXC_CPU_IMX6DL 0x61 17 #define MXC_CPU_IMX6SX 0x62 18 #define MXC_CPU_IMX6Q 0x63 19 #define MXC_CPU_IMX6UL 0x64 20 #define MXC_CPU_IMX6ULL 0x65 22 #define MXC_CPU_IMX6ULZ 0x6b 23 #define MXC_CPU_IMX6SLL 0x67 24 #define MXC_CPU_IMX7D 0x72 25 #define MXC_CPU_IMX7ULP 0xff [all …]
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | jcore,aic.txt | 23 reg = < 0x200 0x30 0x500 0x30 >;
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/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/ |
H A D | mvebu-system-controller.txt | 17 reg = <0xd0018200 0x500>;
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/openbmc/linux/tools/perf/arch/powerpc/util/ |
H A D | book3s_hv_exits.h | 10 {0x0, "RETURN_TO_HOST"}, \ 11 {0x100, "SYSTEM_RESET"}, \ 12 {0x200, "MACHINE_CHECK"}, \ 13 {0x300, "DATA_STORAGE"}, \ 14 {0x380, "DATA_SEGMENT"}, \ 15 {0x400, "INST_STORAGE"}, \ 16 {0x480, "INST_SEGMENT"}, \ 17 {0x500, "EXTERNAL"}, \ 18 {0x502, "EXTERNAL_HV"}, \ 19 {0x600, "ALIGNMENT"}, \ [all …]
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/openbmc/linux/arch/powerpc/kvm/ |
H A D | trace_book3s.h | 10 {0x100, "SYSTEM_RESET"}, \ 11 {0x200, "MACHINE_CHECK"}, \ 12 {0x300, "DATA_STORAGE"}, \ 13 {0x380, "DATA_SEGMENT"}, \ 14 {0x400, "INST_STORAGE"}, \ 15 {0x480, "INST_SEGMENT"}, \ 16 {0x500, "EXTERNAL"}, \ 17 {0x502, "EXTERNAL_HV"}, \ 18 {0x600, "ALIGNMENT"}, \ 19 {0x700, "PROGRAM"}, \ [all …]
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/openbmc/qemu/include/hw/i2c/ |
H A D | microbit_i2c.h | 18 #define NRF51_TWI_TASK_STARTRX 0x000 19 #define NRF51_TWI_TASK_STARTTX 0x008 20 #define NRF51_TWI_TASK_STOP 0x014 21 #define NRF51_TWI_EVENT_STOPPED 0x104 22 #define NRF51_TWI_EVENT_RXDREADY 0x108 23 #define NRF51_TWI_EVENT_TXDSENT 0x11c 24 #define NRF51_TWI_REG_ENABLE 0x500 25 #define NRF51_TWI_REG_RXD 0x518 26 #define NRF51_TWI_REG_TXD 0x51c 27 #define NRF51_TWI_REG_ADDRESS 0x588
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