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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dti,sa2ul.yaml93 reg = <0x4e00000 0x1200>;
95 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
96 <&main_udmap 0x4001>;
/openbmc/u-boot/include/configs/
H A Dmvebu_armada-37xx.h14 #define CONFIG_SYS_SDRAM_BASE 0x00000000
42 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
43 #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
44 #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
45 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
49 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
55 #define CONFIG_SYS_I2C_SLAVE 0x0
65 #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
94 func(MMC, mmc, 0) \
95 func(USB, usb, 0) \
[all …]
H A Dturris_mox.h21 #define CONFIG_SYS_SDRAM_BASE 0x00000000
49 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
50 #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
51 #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
52 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
58 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
64 #define CONFIG_SYS_I2C_SLAVE 0x0
71 #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
86 func(MMC, mmc, 0) \
87 func(USB, usb, 0) \
[all …]
H A Dmvebu_armada-8k.h15 #define CONFIG_SYS_SDRAM_BASE 0x00000000
43 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
44 #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
45 #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
46 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
50 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
56 #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
61 #define CONFIG_SYS_MMC_ENV_DEV 0
100 func(MMC, mmc, 0) \
101 func(USB, usb, 0) \
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a-mcu.dtsi11 reg = <0x00 0x04084000 0x00 0x88>;
14 pinctrl-single,function-mask = <0xffffffff>;
25 reg = <0x00 0x4800000 0x00 0x400>;
35 reg = <0x00 0x4810000 0x00 0x400>;
45 reg = <0x00 0x4820000 0x00 0x400>;
55 reg = <0x00 0x4830000 0x00 0x400>;
65 reg = <0x00 0x04a00000 0x00 0x100>;
68 clocks = <&k3_clks 149 0>;
75 reg = <0x00 0x04900000 0x00 0x100>;
78 #size-cells = <0>;
[all …]
H A Dk3-am62-mcu.dtsi11 reg = <0x00 0x04084000 0x00 0x88>;
14 pinctrl-single,function-mask = <0xffffffff>;
19 reg = <0x00 0x4100000 0x00 0x1000>;
20 ti,esm-pins = <0>, <1>, <2>, <85>;
30 reg = <0x00 0x4800000 0x00 0x400>;
40 reg = <0x00 0x4810000 0x00 0x400>;
50 reg = <0x00 0x4820000 0x00 0x400>;
60 reg = <0x00 0x4830000 0x00 0x400>;
70 reg = <0x00 0x04a00000 0x00 0x100>;
73 clocks = <&k3_clks 149 0>;
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-j784s4-main.dtsi11 reg = <0x00 0x70000000 0x00 0x800000>;
14 ranges = <0x00 0x00 0x70000000 0x800000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
21 reg = <0x1f0000 0x10000>;
25 reg = <0x200000 0x200000>;
36 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
37 <0x00 0x01900000 0x00 0x100000>, /* GICR */
38 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
39 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]