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/openbmc/u-boot/arch/mips/dts/
H A Dci20.dts23 reg = <0x0 0x10000000
24 0x30000000 0x30000000>;
53 reg = <1 0 0x1000000>;
56 #size-cells = <0>;
79 partition@0 {
81 reg = <0x0 0x0 0x0 0x800000>;
84 partition@0x800000 {
86 reg = <0x0 0x800000 0x0 0x200000>;
89 partition@0xa00000 {
91 reg = <0x0 0xa00000 0x0 0x200000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Ddragonboard820c.dts29 reg = <0 0x80000000 0 0xc0000000>;
38 reg = <0x0 0x86300000 0x0 0x200000>;
56 ranges = <0 0 0 0xffffffff>;
64 reg = <0x300000 0x90000>;
69 reg = <0x1010000 0x400000>;
81 reg = <0x75b0000 0x1000>;
84 pinctrl-0 = <&blsp8_uart>;
89 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
90 index = <0x0>;
92 clock = <&gcc 0>;
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dci20.dts27 reg = <0x0 0x10000000
28 0x30000000 0x30000000>;
45 led-0 {
65 gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
70 eth0_power: fixedregulator-0 {
77 gpio = <&gpb 25 0>;
110 gpio = <&gpb 19 0>;
121 gpio = <&gpf 15 0>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
[all …]