Searched +full:0 +full:x4a030000 (Results 1 – 4 of 4) sorted by relevance
19 0x0200 or above.21 enum: [0x0100, 0x0120, 0x0130, 0x0200]71 reg = <0x4a030000 0xcfff>;72 interrupts = <0 92 4>;77 otg-rev = <0x0200>;
188 - 0 # -6dB de-emphasis264 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end299 minimum: 0300 maximum: 0x3f393 port@0:417 reg = <0x4a030000 0xcfff>;418 interrupts = <0 92 4>;425 reg = <0x4a000000 0xcfff>;426 interrupts = <0 92 4>;
14 #define OMAP_XHCI_BASE 0x488d000015 #define OMAP_OCP1_SCP_BASE 0x4A08100016 #define OMAP_OTG_WRAPPER_BASE 0x488c000017 #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 018 #define OMAP_XHCI_BASE 0x4889000019 #define OMAP_OCP1_SCP_BASE 0x4A084c0020 #define OMAP_OTG_WRAPPER_BASE 0x4888000023 #define OMAP_XHCI_BASE 0x483d000024 #define OMAP_OCP1_SCP_BASE 0x483E800025 #define OMAP_OTG_WRAPPER_BASE 0x483dc100[all …]
23 #define OMAP54XX_L4_CORE_BASE 0x4A00000024 #define OMAP54XX_L4_WKUP_BASE 0x4Ae0000025 #define OMAP54XX_L4_PER_BASE 0x4800000028 #define CONTROL_CORE_ID_CODE 0x4A00220429 #define CONTROL_WKUP_ID_CODE 0x4AE0C20438 #define DRA7_USB_OTG_SS1_BASE 0x4889000039 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x4888000040 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C0041 #define DRA7_USB3_PHY1_POWER 0x4A00237042 #define DRA7_USB2_PHY1_POWER 0x4A002300[all …]