Searched +full:0 +full:x46200000 (Results 1 – 5 of 5) sorted by relevance
45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and78 // mapped to 0x43f00000 of the parent bus.79 // - the UART device is connected at the offset 0x00200000 of CS5 and80 // mapped to 0x46200000 of the parent bus.84 reg = <0x58c00000 0x400>;[all …]
14 #size-cells = <0>;16 cpu0: cpu@0 {19 reg = <0>;33 #clock-cells = <0>;39 #clock-cells = <0>;45 #clock-cells = <0>;60 #size-cells = <0>;61 linaro,optee-channel-id = <0>;64 reg = <0x14>;69 reg = <0x16>;[all …]
23 #clock-cells = <0>;30 #clock-cells = <0>;38 #size-cells = <0>;40 CPU0: cpu@0 {43 reg = <0x0 0x0>;57 reg = <0x0 0x1>;66 reg = <0x0 0x2>;75 reg = <0x0 0x3>;84 reg = <0x0 0x100>;98 reg = <0x0 0x101>;[all …]
27 #clock-cells = <0>;32 #clock-cells = <0>;38 #size-cells = <0>;40 CPU0: cpu@0 {43 reg = <0x0 0x0>;44 clocks = <&cpufreq_hw 0>;49 qcom,freq-domain = <&cpufreq_hw 0>;62 reg = <0x0 0x1>;63 clocks = <&cpufreq_hw 0>;68 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
82 #define OP_MASK_OP 0x3f84 #define OP_MASK_RS 0x1f86 #define OP_MASK_FR 0x1f88 #define OP_MASK_FMT 0x1f90 #define OP_MASK_BCC 0x792 #define OP_MASK_CODE 0x3ff94 #define OP_MASK_CODE2 0x3ff96 #define OP_MASK_RT 0x1f98 #define OP_MASK_FT 0x1f100 #define OP_MASK_CACHE 0x1f[all …]