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/openbmc/linux/arch/arm/mach-imx/
H A Dhardware.h21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
43 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
44 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
45 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
47 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
48 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
51 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
H A Dmx31.h5 #define MX31_AIPS1_BASE_ADDR 0x43f00000
7 #define MX31_SPBA0_BASE_ADDR 0x50000000
9 #define MX31_AIPS2_BASE_ADDR 0x53f00000
11 #define MX31_AVIC_BASE_ADDR 0x68000000
13 #define MX31_X_MEMC_BASE_ADDR 0xb8000000
H A Dmx35.h5 #define MX35_AIPS1_BASE_ADDR 0x43f00000
7 #define MX35_SPBA0_BASE_ADDR 0x50000000
9 #define MX35_AIPS2_BASE_ADDR 0x53f00000
11 #define MX35_AVIC_BASE_ADDR 0x68000000
13 #define MX35_X_MEMC_BASE_ADDR 0xb8000000
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/sbc/
H A Dsbc.c13 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
14 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
15 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
17 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
18 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
19 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
22 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
23 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
24 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
25 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dmemmap-gen3.c15 .virt = 0x0UL,
16 .phys = 0x0UL,
17 .size = 0x40000000UL,
22 .virt = 0x40000000UL,
23 .phys = 0x40000000UL,
24 .size = 0x03F00000UL,
28 .virt = 0x47E00000UL,
29 .phys = 0x47E00000UL,
30 .size = 0x78200000UL,
34 .virt = 0xc0000000UL,
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmicro-support-card.c14 #define MICRO_SUPPORT_CARD_BASE 0x43f00000
15 #define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
16 #define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
17 #define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
18 #define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
19 #define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
22 * 0: reset deassert, 1: reset
24 * bit[0]: LAN, I2C, LED
29 writel(0x00010000, MICRO_SUPPORT_CARD_RESET); in support_card_reset_deassert()
34 writel(0x00020003, MICRO_SUPPORT_CARD_RESET); in support_card_reset()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25.dtsi47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
60 reg = <0x68000000 0x8000000>;
66 #clock-cells = <0>;
82 reg = <0x43f00000 0x100000>;
87 reg = <0x43f00000 0x4000>;
92 #size-cells = <0>;
94 reg = <0x43f80000 0x4000>;
103 #size-cells = <0>;
[all …]
H A Dimx31.dtsi35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0>;
48 reg = <0x68000000 0x100000>;
60 reg = <0x1fffc000 0x4000>;
63 ranges = <0 0x1fffc000 0x4000>;
70 reg = <0x43f00000 0x100000>;
75 reg = <0x43f80000 0x4000>;
79 #size-cells = <0>;
85 reg = <0x43f84000 0x4000>;
[all …]
H A Dimx35.dtsi39 #size-cells = <0>;
41 cpu@0 {
44 reg = <0>;
52 reg = <0x68000000 0x10000000>;
64 reg = <0x30000000 0x1000>;
73 reg = <0x43f00000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x43f80000 0x4000>;
89 #size-cells = <0>;
91 reg = <0x43f84000 0x4000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dimx-regs.h16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */
17 #define IRAM_SIZE 0x00020000 /* 128 KB */
19 #define LOW_LEVEL_SRAM_STACK 0x1001E000
24 #define AIPS1_BASE_ADDR 0x43F00000
26 #define MAX_BASE_ADDR 0x43F04000
27 #define EVTMON_BASE_ADDR 0x43F08000
28 #define CLKCTL_BASE_ADDR 0x43F0C000
29 #define I2C1_BASE_ADDR 0x43F80000
30 #define I2C3_BASE_ADDR 0x43F84000
31 #define ATA_BASE_ADDR 0x43F8C000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h27 u32 cgr0; /* Clock Gating Control 0 */
33 u32 dcvr0; /* DPTC Comparator Value 0 */
37 u32 ltr0; /* Load Tracking 0 */
41 u32 ltbr0; /* Load Tracking Buffer 0 */
43 u32 pcmr0; /* Power Management Control 0 */
47 u32 lpimr0; /* Low Power Interrupt Mask 0 */
53 u32 ctl0; /* control 0 */
54 u32 cfg0; /* configuration 0 */
104 u32 res1[0x1f1];
106 u32 fuse_regs[0x20];
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx31/
H A Dimx-regs.h70 u32 res[0x1f1];
72 u32 fuse_regs[0x20];
73 u32 fuse_rsvd[0xe0];
100 #define IOMUX_PADNUM_MASK 0x1ff
107 PAD_CTL_NOLOOPBACK = 0x0 << 9,
108 PAD_CTL_LOOPBACK = 0x1 << 9,
109 PAD_CTL_PKE_NONE = 0x0 << 8,
110 PAD_CTL_PKE_ENABLE = 0x1 << 8,
111 PAD_CTL_PUE_KEEPER = 0x0 << 7,
112 PAD_CTL_PUE_PUD = 0x1 << 7,
[all …]
/openbmc/linux/sound/pci/hda/
H A Dpatch_ca0132.c37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
55 #define MASTERCONTROL 0x80
[all …]