Searched +full:0 +full:x43100000 (Results 1 – 7 of 7) sorted by relevance
8 #define PXA_CS0_PHYS 0x000000009 #define PXA_CS1_PHYS 0x0400000010 #define PXA_CS2_PHYS 0x0800000011 #define PXA_CS3_PHYS 0x0C00000012 #define PXA_CS4_PHYS 0x1000000013 #define PXA_CS5_PHYS 0x1400000015 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */17 #define PXA3xx_CS2_PHYS 0x1000000018 #define PXA3xx_CS3_PHYS 0x14000000[all …]
66 minimum: 071 - minimum: 0156 reg = <0xd0000 0x54>;158 #size-cells = <0>;160 clocks = <&coredivclk 0>;162 nand@0 {163 reg = <0>;165 nand-rb = <0>;177 partition@0 {179 reg = <0x00000000 0x40000000>;[all …]
6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \10 0)12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \14 0)17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \[all …]
77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */83 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */88 #define CONFIG_SYS_IMMR 0xE000000094 #define CONFIG_FSL_SERDES1 0xe3000106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */115 /* 0x7b880001 */123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007129 /* 0x80010102 */130 #define CONFIG_SYS_DDR_TIMING_3 0131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \[all …]
77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */83 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */88 #define CONFIG_SYS_IMMR 0xE000000094 #define CONFIG_FSL_SERDES1 0xe3000106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */115 /* 0x7b880001 */123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007129 /* 0x80010102 */130 #define CONFIG_SYS_DDR_TIMING_3 0131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \[all …]
37 #define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */38 #define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */39 #define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */40 #define PXA_CS2_PHYS 0x10000000 /* (64MB) */41 #define PXA_CS3_PHYS 0x14000000 /* (64MB) */42 #define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */44 #define PXA_CS0_PHYS 0x0000000045 #define PXA_CS1_PHYS 0x0400000046 #define PXA_CS2_PHYS 0x0800000047 #define PXA_CS3_PHYS 0x0C000000[all …]
37 #define FLOAT_ZERO 0x0000000038 #define FLOAT_ONE 0x3f80000039 #define FLOAT_TWO 0x4000000040 #define FLOAT_THREE 0x4040000041 #define FLOAT_FIVE 0x40a0000042 #define FLOAT_SIX 0x40c0000043 #define FLOAT_EIGHT 0x4100000044 #define FLOAT_MINUS_5 0xc0a0000046 #define UNSOL_TAG_DSP 0x1655 #define MASTERCONTROL 0x80[all …]