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Searched +full:0 +full:x41410000 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_specs_40x.h8 .pvr_mask = 0xffff0000,
9 .pvr_value = 0x41810000,
21 .pvr_mask = 0xffff0000,
22 .pvr_value = 0x41610000,
34 .pvr_mask = 0xffff0000,
35 .pvr_value = 0x40B10000,
47 .pvr_mask = 0xffff0000,
48 .pvr_value = 0x41410000,
60 .pvr_mask = 0xffff0000,
61 .pvr_value = 0x50910000,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on
76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and
103 either of them can be configured to appear at that R5F's address 0x0.
177 enum: [0, 1]
181 either a value of 1 (enabled) or 0 (disabled), default is disabled
186 enum: [0, 1]
190 either a value of 1 (enabled) or 0 (disabled), default is enabled if
195 enum: [0, 1]
198 address 0 (from core's view). Should be either a value of 1 (ATCM
199 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
26 reg = <0x0 0x40f04200 0x0 0x10>;
29 pinctrl-single,function-mask = <0x00000101>;
35 reg = <0x0 0x40f04280 0x0 0x8>;
38 pinctrl-single,function-mask = <0x00000003>;
43 reg = <0x00 0x40a00000 0x00 0x100>;
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi20 reg = <0x00 0x44083000 0x00 0x1000>;
44 reg = <0x00 0x43000014 0x00 0x4>;
51 reg = <0x00 0x43600000 0x00 0x10000>,
52 <0x00 0x44880000 0x00 0x20000>,
53 <0x00 0x44860000 0x00 0x20000>;
64 reg = <0x00 0x41c00000 0x00 0x100000>;
65 ranges = <0x00 0x00 0x41c00000 0x100000>;
72 /* Proxy 0 addressing */
73 reg = <0x00 0x4301c000 0x00 0x034>;
76 pinctrl-single,function-mask = <0xffffffff>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
68 reg = <0x00 0x40f04200 0x00 0x28>;
71 pinctrl-single,function-mask = <0x0000000f>;
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg.h49 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
54 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
61 #define MSR_LE_LG 0 /* Little Endian */
75 #define MSR_SF 0
76 #define MSR_HV 0
77 #define MSR_S 0
85 #define MSR_SPE 0
99 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
104 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
116 #define MSR_TS_N 0 /* Non-transactional */
[all …]
/openbmc/u-boot/arch/x86/dts/microcode/
H A Dm0230671117.dtsi11 intel,update-revision = <0x117>;
12 intel,date-code = <0x4102013>;
13 intel,processor-signature = <0x30671>;
14 intel,checksum = <0x2abfd907>;
16 intel,processor-flags = <0x2>;
20 0x01000000 0x17010000 0x13201004 0x71060300
21 0x07d9bf2a 0x01000000 0x02000000 0xd0070100
22 0x00080100 0x00000000 0x00000000 0x00000000
23 0x00000000 0xa1000000 0x01000200 0x17010000
24 0x00000000 0x00000000 0x09041320 0x41410000
[all …]