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/openbmc/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dirqflags-compact.h33 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
34 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
35 #define AUX_IRQ_LV12 0x43 /* interrupt level register */
37 #define AUX_IENABLE 0x40c
38 #define AUX_ITRIGGER 0x40d
39 #define AUX_IPULSE 0x415
71 " bic %0, %1, %2 \n" in arch_local_irq_save()
72 " and.f 0, %1, %2 \n" in arch_local_irq_save()
73 " flag.nz %0 \n" in arch_local_irq_save()
88 " flag %0 \n" in arch_local_irq_restore()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
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/openbmc/u-boot/drivers/net/
H A Dmtk_eth.h13 #define PDMA_BASE 0x0800
14 #define GDMA1_BASE 0x0500
15 #define GDMA2_BASE 0x1500
16 #define GMAC_BASE 0x10000
20 #define ETHSYS_SYSCFG0_REG 0x14
22 #define SYSCFG0_GE_MODE_M 0x3
24 #define ETHSYS_CLKCFG0_REG 0x2c
28 #define GE_MODE_RGMII 0
36 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
37 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
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/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lcn.c66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup()
67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup()
70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup()
71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup()
72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup()
73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup()
74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup()
75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup()
76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup()
77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup()
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/openbmc/linux/tools/testing/selftests/arm64/fp/
H A Dzt-ptrace.c25 #define NT_ARM_ZA 0x40c
28 #define NT_ARM_ZT 0x40d
39 for (i = 0; i < size; i++) in fill_buf()
128 memset(&za, 0, sizeof(za)); in ptrace_za_disabled_read_zt()
133 if (ret != 0) { in ptrace_za_disabled_read_zt()
140 if (ret != 0) { in ptrace_za_disabled_read_zt()
145 for (i = 0; i < ARRAY_SIZE(zt); i++) { in ptrace_za_disabled_read_zt()
147 ksft_print_msg("zt[%d]: 0x%x != 0\n", i, zt[i]); in ptrace_za_disabled_read_zt()
166 if (ret != 0) { in ptrace_set_get_zt()
172 if (ret != 0) { in ptrace_set_get_zt()
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/openbmc/linux/include/uapi/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
39 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
40 #define PT_GNU_RELRO (PT_LOOS + 0x474e552)
41 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
45 #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_lcn.c40 #define NOISE_IF_OFF 0
45 #define PAPD2LUT 0
46 #define PAPD_CORR_NORM 0
47 #define PAPD_BLANKING_THRESHOLD 0
48 #define PAPD_STOP_AFTER_LAST_UPDATE 0
70 (0 + 8)
72 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
75 (0 + 8)
77 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
85 (read_phy_reg((pi), 0x451) & \
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/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/openbmc/qemu/hw/usb/
H A Dhcd-dwc3.c41 #define USB_DWC3_ERR_DEBUG 0
45 #define FIFO_LEN 0x1000
47 REG32(GSBUSCFG0, 0x00)
63 FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1)
64 REG32(GSBUSCFG1, 0x04)
68 FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8)
69 REG32(GTXTHRCFG, 0x08)
79 FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11)
80 REG32(GRXTHRCFG, 0x0c)
89 FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13)
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dmt7530.h12 #define MT7530_ALL_MEMBERS 0xff
18 ID_MT7530 = 0,
26 #define TRGMII_BASE(x) (0x10000 + (x))
29 #define ETHSYS_CLKCFG0 0x2c
32 #define SYSC_REG_RSTCTRL 0x34
36 #define MT753X_AGC 0xc
40 #define MT7530_MFC 0x10
41 #define BC_FFP(x) (((x) & 0xff) << 24)
42 #define BC_FFP_MASK BC_FFP(~0)
43 #define UNM_FFP(x) (((x) & 0xff) << 16)
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Drtl2832.c14 [DVBT_SOFT_RST] = {0x101, 2, 2},
15 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
16 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
17 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
18 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
19 [DVBT_AD_EN_REG] = {0x008, 7, 7},
20 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
21 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
22 [DVBT_MGD_THD0] = {0x195, 7, 0},
23 [DVBT_MGD_THD1] = {0x196, 7, 0},
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.c17 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write()
18 u32 mask = 0xff; in cx18_av_write()
24 return 0; in cx18_av_write()
29 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write_expect()
33 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); in cx18_av_write_expect()
36 return 0; in cx18_av_write_expect()
41 cx18_write_reg(cx, value, 0xc40000 + addr); in cx18_av_write4()
42 return 0; in cx18_av_write4()
48 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); in cx18_av_write4_expect()
49 return 0; in cx18_av_write4_expect()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8962.h16 #define WM8962_SYSCLK_MCLK 0
30 #define WM8962_LEFT_INPUT_VOLUME 0x00
31 #define WM8962_RIGHT_INPUT_VOLUME 0x01
32 #define WM8962_HPOUTL_VOLUME 0x02
33 #define WM8962_HPOUTR_VOLUME 0x03
34 #define WM8962_CLOCKING1 0x04
35 #define WM8962_ADC_DAC_CONTROL_1 0x05
36 #define WM8962_ADC_DAC_CONTROL_2 0x06
37 #define WM8962_AUDIO_INTERFACE_0 0x07
38 #define WM8962_CLOCKING2 0x08
[all …]
H A Dwm2200.h14 #define WM2200_CLKSRC_MCLK1 0
19 #define WM2200_FLL_SRC_MCLK1 0
26 #define WM2200_SOFTWARE_RESET 0x00
27 #define WM2200_DEVICE_REVISION 0x01
28 #define WM2200_TONE_GENERATOR_1 0x0B
29 #define WM2200_CLOCKING_3 0x102
30 #define WM2200_CLOCKING_4 0x103
31 #define WM2200_FLL_CONTROL_1 0x111
32 #define WM2200_FLL_CONTROL_2 0x112
33 #define WM2200_FLL_CONTROL_3 0x113
[all …]
/openbmc/linux/fs/smb/client/
H A Dcifspdu.h16 #define CIFS_PROT 0
18 #define BAD_PROT 0xFFFF
21 * Note some commands have minimal (wct=0,bcc=0), or uninteresting, responses
25 #define SMB_COM_CREATE_DIRECTORY 0x00 /* trivial response */
26 #define SMB_COM_DELETE_DIRECTORY 0x01 /* trivial response */
27 #define SMB_COM_CLOSE 0x04 /* triv req/rsp, timestamp ignored */
28 #define SMB_COM_FLUSH 0x05 /* triv req/rsp */
29 #define SMB_COM_DELETE 0x06 /* trivial response */
30 #define SMB_COM_RENAME 0x07 /* trivial response */
31 #define SMB_COM_QUERY_INFORMATION 0x08 /* aka getattr */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dcore.h22 #define MASKBYTE0 0xff
23 #define MASKBYTE1 0xff00
24 #define MASKBYTE2 0xff0000
25 #define MASKBYTE3 0xff000000
26 #define MASKBYTE4 0xff00000000ULL
27 #define MASKHWORD 0xffff0000
28 #define MASKLWORD 0x0000ffff
29 #define MASKDWORD 0xffffffff
30 #define RFREG_MASK 0xfffff
31 #define INV_RF_DATA 0xffffffff
[all …]
/openbmc/linux/drivers/hwmon/
H A Dnct6775-core.c22 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
23 * nct6116d 9 5 5 3+3 0xd280 0xc1 0x5ca3
24 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
25 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
26 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
27 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
28 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
29 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
30 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
31 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
[all …]
/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-core.c45 #define CX25840_VID_INT_STAT_REG 0x410
46 #define CX25840_VID_INT_STAT_BITS 0x0000ffff
47 #define CX25840_VID_INT_MASK_BITS 0xffff0000
49 #define CX25840_VID_INT_MASK_REG 0x412
51 #define CX23885_AUD_MC_INT_MASK_REG 0x80c
52 #define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
53 #define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
56 #define CX25840_AUD_INT_CTRL_REG 0x812
57 #define CX25840_AUD_INT_STAT_REG 0x813
59 #define CX23885_PIN_CTRL_IRQ_REG 0x123
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate.c64 for (i = 0; i < 16; i++) { in arm_translate_init()
86 case 0: case 1: in asimd_imm_const()
105 imm = (imm << 8) | 0xff; in asimd_imm_const()
108 imm = (imm << 16) | 0xffff; in asimd_imm_const()
116 uint64_t imm64 = 0; in asimd_imm_const()
119 for (n = 0; n < 8; n++) { in asimd_imm_const()
121 imm64 |= (0xffULL << (n * 8)); in asimd_imm_const()
131 uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; in asimd_imm_const()
132 if (imm & 0x80) { in asimd_imm_const()
133 imm64 |= 0x8000000000000000ULL; in asimd_imm_const()
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "MMID", 89, 0 },
36 { "DDR", 104, 0 },
37 { "176", 176, 0 },
38 { "208", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]