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/openbmc/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dmmu-arcv2.h15 #define ARC_REG_MMU_BCR 0x06f
18 #define ARC_REG_TLBPD0 0x405
19 #define ARC_REG_TLBPD1 0x406
20 #define ARC_REG_TLBPD1HI 0 /* Dummy: allows common code */
21 #define ARC_REG_TLBINDEX 0x407
22 #define ARC_REG_TLBCOMMAND 0x408
23 #define ARC_REG_PID 0x409
24 #define ARC_REG_SCRATCH_DATA0 0x418
26 #define ARC_REG_TLBPD0 0x460
27 #define ARC_REG_TLBPD1 0x461
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_sl82c105.c33 * SL82C105 PCI config register 0x40 bits.
41 CTRL_P0EN = (1 << 0)
55 { 0x40, 1, 0x01, 0x01 }, in sl82c105_pre_reset()
56 { 0x40, 1, 0x10, 0x10 } in sl82c105_pre_reset()
82 0x50D, 0x407, 0x304, 0x242, 0x240 in sl82c105_configure_piomode()
85 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); in sl82c105_configure_piomode()
119 0x707, 0x201, 0x200 in sl82c105_configure_dmamode()
122 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); in sl82c105_configure_dmamode()
145 pci_read_config_word(pdev, 0x7E, &val); in sl82c105_reset_engine()
146 pci_write_config_word(pdev, 0x7E, val | 4); in sl82c105_reset_engine()
[all …]
/openbmc/linux/drivers/perf/
H A Dqcom_l2_pmu.c31 #define L2PMCR_NUM_EV_MASK 0x1F
33 #define L2PMCR 0x400
34 #define L2PMCNTENCLR 0x403
35 #define L2PMCNTENSET 0x404
36 #define L2PMINTENCLR 0x405
37 #define L2PMINTENSET 0x406
38 #define L2PMOVSCLR 0x407
39 #define L2PMOVSSET 0x408
40 #define L2PMCCNTCR 0x409
41 #define L2PMCCNTR 0x40A
[all …]
/openbmc/linux/include/uapi/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
39 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
40 #define PT_GNU_RELRO (PT_LOOS + 0x474e552)
41 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
45 #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
[all …]
/openbmc/linux/drivers/platform/x86/
H A Dlg-laptop.c43 #define GOV_TLED 0x2020008
46 #define WM_KEY_LIGHT 0x400
47 #define WM_TLED 0x404
48 #define WM_FN_LOCK 0x407
49 #define WM_BATT_LIMIT 0x61
50 #define WM_READER_MODE 0xBF
51 #define WM_FAN_MODE 0x33
52 #define WMBB_USB_CHARGE 0x10B
53 #define WMBB_BATT_LIMIT 0x10C
68 #define INIT_INPUT_WMI_0 0x01
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c37 #define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0
40 REG32(MIO_PIN_0, 0x0)
45 REG32(MIO_PIN_1, 0x4)
50 REG32(MIO_PIN_2, 0x8)
55 REG32(MIO_PIN_3, 0xc)
60 REG32(MIO_PIN_4, 0x10)
65 REG32(MIO_PIN_5, 0x14)
70 REG32(MIO_PIN_6, 0x18)
75 REG32(MIO_PIN_7, 0x1c)
80 REG32(MIO_PIN_8, 0x20)
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
[all …]
/openbmc/linux/include/linux/mfd/
H A Dtps6594.h26 /* Registers for page 0 of TPS6594 */
27 #define TPS6594_REG_DEV_REV 0x01
29 #define TPS6594_REG_NVM_CODE_1 0x02
30 #define TPS6594_REG_NVM_CODE_2 0x03
32 #define TPS6594_REG_BUCKX_CTRL(buck_inst) (0x04 + ((buck_inst) << 1))
33 #define TPS6594_REG_BUCKX_CONF(buck_inst) (0x05 + ((buck_inst) << 1))
34 #define TPS6594_REG_BUCKX_VOUT_1(buck_inst) (0x0e + ((buck_inst) << 1))
35 #define TPS6594_REG_BUCKX_VOUT_2(buck_inst) (0x0f + ((buck_inst) << 1))
36 #define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst) (0x18 + (buck_inst))
38 #define TPS6594_REG_LDOX_CTRL(ldo_inst) (0x1d + (ldo_inst))
[all …]
/openbmc/linux/sound/pci/lx6464es/
H A Dlx_core.c23 0,
24 0x400,
25 0x401,
26 0x402,
27 0x403,
28 0x404,
29 0x405,
30 0x406,
31 0x407,
32 0x408,
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Ddas16.c33 * [0] - base io address
71 #define DAS16_DMA_SIZE 0xff00 /* size in bytes of allocated dma buffer */
76 #define DAS16_TRIG_REG 0x00
77 #define DAS16_AI_LSB_REG 0x00
78 #define DAS16_AI_MSB_REG 0x01
79 #define DAS16_MUX_REG 0x02
80 #define DAS16_DIO_REG 0x03
81 #define DAS16_AO_LSB_REG(x) ((x) ? 0x06 : 0x04)
82 #define DAS16_AO_MSB_REG(x) ((x) ? 0x07 : 0x05)
83 #define DAS16_STATUS_REG 0x08
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_venc.c13 MESON_VENC_MODE_NONE = 0,
20 MESON_VENC_SOURCE_NONE = 0,
25 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
26 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
59 .video_prog_mode = 0xff,
60 .video_mode = 0x13,
61 .sch_adjust = 0x28,
62 .yc_delay = 0x343,
70 .video_contrast = 0,
71 .video_brightness = 0,
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dcirrusfb.c90 BT_NONE = 0,
134 135100, 135100, 85500, 85500, 0
139 .sr07 = 0xF0,
140 .sr07_1bpp = 0xF0,
141 .sr07_1bpp_mux = 0xF6,
142 .sr07_8bpp = 0xF1,
143 .sr07_8bpp_mux = 0xF7,
144 .sr1f = 0x1E
155 .sr07 = 0x80,
156 .sr07_1bpp = 0x80,
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c64 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
65 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
66 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */
67 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
68 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */
69 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
78 .video_prog_mode = 0xff,
79 .video_mode = 0x13,
80 .sch_adjust = 0x28,
81 .yc_delay = 0x343,
[all …]
/openbmc/linux/drivers/net/wireless/st/cw1200/
H A Dwsm.c32 } while (0)
40 } while (0)
63 } while (0)
72 } while (0)
98 return 0; in wsm_generic_confirm()
149 for (i = 0; i < 2; ++i) { in wsm_configuration_confirm()
154 return 0; in wsm_configuration_confirm()
171 WSM_PUT32(buf, arg->reset_statistics ? 0 : 1); in wsm_reset()
202 WSM_PUT16(buf, 0); in wsm_read_mib()
231 return 0; in wsm_read_mib_confirm()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
/openbmc/linux/drivers/hwmon/
H A Dnct6775-core.c22 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
23 * nct6116d 9 5 5 3+3 0xd280 0xc1 0x5ca3
24 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
25 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
26 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
27 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
28 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
29 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
30 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
31 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
[all …]
/openbmc/linux/fs/smb/client/
H A Dcifspdu.h16 #define CIFS_PROT 0
18 #define BAD_PROT 0xFFFF
21 * Note some commands have minimal (wct=0,bcc=0), or uninteresting, responses
25 #define SMB_COM_CREATE_DIRECTORY 0x00 /* trivial response */
26 #define SMB_COM_DELETE_DIRECTORY 0x01 /* trivial response */
27 #define SMB_COM_CLOSE 0x04 /* triv req/rsp, timestamp ignored */
28 #define SMB_COM_FLUSH 0x05 /* triv req/rsp */
29 #define SMB_COM_DELETE 0x06 /* trivial response */
30 #define SMB_COM_RENAME 0x07 /* trivial response */
31 #define SMB_COM_QUERY_INFORMATION 0x08 /* aka getattr */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8995.h18 #define WM8995_SOFTWARE_RESET 0x00
19 #define WM8995_POWER_MANAGEMENT_1 0x01
20 #define WM8995_POWER_MANAGEMENT_2 0x02
21 #define WM8995_POWER_MANAGEMENT_3 0x03
22 #define WM8995_POWER_MANAGEMENT_4 0x04
23 #define WM8995_POWER_MANAGEMENT_5 0x05
24 #define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
25 #define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
26 #define WM8995_LEFT_LINE_INPUT_CONTROL 0x12
27 #define WM8995_DAC1_LEFT_VOLUME 0x18
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]

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