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/openbmc/linux/Documentation/devicetree/bindings/media/cec/
H A Dst,stm32-cec.yaml47 reg = <0x40006c00 0x400>;
/openbmc/qemu/hw/arm/
H A Dstm32f100_soc.c39 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
40 0x40004800 };
41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
53 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f100_soc_initfn()
58 for (i = 0; i < STM_NUM_SPIS; i++) { in stm32f100_soc_initfn()
62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize()
106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize()
108 memory_region_add_subregion(system_memory, 0, &s->flash_alias); in stm32f100_soc_realize()
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
[all …]
/openbmc/linux/drivers/bus/
H A Dti-sysc.c30 #define DIS_SGX BIT(0)
167 writew_relaxed(value & 0xffff, ddata->module_va + offset); in sysc_write()
170 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_write()
191 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_read()
213 if (offset < 0) in sysc_read_revision()
214 return 0; in sysc_read_revision()
223 if (offset < 0) in sysc_read_sysconfig()
224 return 0; in sysc_read_sysconfig()
233 if (offset < 0) in sysc_read_sysstatus()
234 return 0; in sysc_read_sysstatus()
[all …]