Searched +full:0 +full:x3f1a0000 (Results 1 – 5 of 5) sorted by relevance
8 #define BSC1_BASE_ADDR 0x3e0160009 #define BSC2_BASE_ADDR 0x3e01700010 #define BSC3_BASE_ADDR 0x3e01800011 #define GPIO2_BASE_ADDR 0x3500300012 #define HSOTG_BASE_ADDR 0x3f12000013 #define HSOTG_CTRL_BASE_ADDR 0x3f13000014 #define KONA_MST_CLK_BASE_ADDR 0x3f00100015 #define KONA_SLV_CLK_BASE_ADDR 0x3e01100016 #define PMU_BSC_BASE_ADDR 0x3500d00017 #define SDIO1_BASE_ADDR 0x3f180000[all …]
8 #define BSC1_BASE_ADDR 0x3e0160009 #define BSC2_BASE_ADDR 0x3e01700010 #define BSC3_BASE_ADDR 0x3e01800011 #define DWDMA_AHB_BASE_ADDR 0x3810000012 #define ESUB_CLK_BASE_ADDR 0x3800000013 #define ESW_CONTRL_BASE_ADDR 0x3820000014 #define GPIO2_BASE_ADDR 0x3500300015 #define HSOTG_BASE_ADDR 0x3f12000016 #define HSOTG_CTRL_BASE_ADDR 0x3f13000017 #define KONA_MST_CLK_BASE_ADDR 0x3f001000[all …]
44 reg = <0x3f1a0000 0x10000>;
21 #size-cells = <0>;23 cpu0: cpu@0 {26 reg = <0>;33 secondary-boot-reg = <0x35004178>;41 #address-cells = <0>;43 reg = <0x3ff01000 0x1000>,44 <0x3ff00100 0x100>;49 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */54 reg = <0x3e000000 0x118>;64 reg = <0x3e001000 0x118>;[all …]
21 #size-cells = <0>;23 cpu0: cpu@0 {26 reg = <0>;33 secondary-boot-reg = <0x3500417c>;41 #address-cells = <0>;43 reg = <0x3ff01000 0x1000>,44 <0x3ff00100 0x100>;49 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */54 reg = <0x3e000000 0x1000>;64 reg = <0x3e001000 0x1000>;[all …]