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/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00ffffffffffffffff) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00ffffffffffffffff) (OK)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
19 to uint64: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
21 to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (OK)
[all …]
/openbmc/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fff4000000000000) (OK)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
13 to uint64: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dk3-ringacc.yaml84 reg = <0x0 0x3c000000 0x0 0x400000>,
85 <0x0 0x38000000 0x0 0x400000>,
86 <0x0 0x31120000 0x0 0x100>,
87 <0x0 0x33000000 0x0 0x40000>,
88 <0x0 0x31080000 0x0 0x40000>;
91 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
/openbmc/u-boot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c15 #define ETH_PHY_CTRL_REG 0
21 * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
38 #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
42 #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
47 writel(0x00000000, MVEBU_MPP_BASE + 0x00); in board_early_init_f()
48 writel(0x00000000, MVEBU_MPP_BASE + 0x04); in board_early_init_f()
49 writel(0x33000000, MVEBU_MPP_BASE + 0x08); in board_early_init_f()
50 writel(0x11000000, MVEBU_MPP_BASE + 0x0c); in board_early_init_f()
51 writel(0x11111111, MVEBU_MPP_BASE + 0x10); in board_early_init_f()
52 writel(0x00221100, MVEBU_MPP_BASE + 0x14); in board_early_init_f()
[all …]
/openbmc/u-boot/include/configs/
H A Dsmdkc100.h30 #define CONFIG_SYS_SDRAM_BASE 0x30000000
40 * 1MB = 0x100000, 0x100000 = 1024 * 1024
64 #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
65 " onenand write 0x32008000 0x0 0x40000\0"
71 "onenand erase 0x60000 0x300000;" \
72 "onenand write 0x31008000 0x60000 0x300000\0" \
75 "onenand write 0x32000000 0x1260000 0x8C0000\0" \
77 "onenand read 0x30007FC0 0x60000 0x300000;" \
78 "bootm 0x30007FC0\0" \
83 "run bootk\0" \
[all …]
H A Ds5p_goni.h27 #define CONFIG_SYS_SDRAM_BASE 0x30000000
55 #define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
56 #define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
57 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
58 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
72 "u-boot raw 0x80 0x400;" \
73 "uImage ext4 0 2;" \
74 "exynos3-goni.dtb ext4 0 2;" \
75 ""PARTS_ROOT" part 0 5\0"
86 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffe00000)
3 to double: f64(-nan:0x00fffc000000000000) (OK)
6 to uint32: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
[all …]
/openbmc/qemu/tests/tcg/x86_64/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
6 to uint32: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
[all …]
/openbmc/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dimx-regs.h11 #define ROM_VERSION_A0 0x800
12 #define ROM_VERSION_B0 0x83C
14 #define M4_BOOTROM_BASE_ADDR 0x007E0000
16 #define SAI1_BASE_ADDR 0x30010000
17 #define SAI6_BASE_ADDR 0x30030000
18 #define SAI5_BASE_ADDR 0x30040000
19 #define SAI4_BASE_ADDR 0x30050000
20 #define SPBA2_BASE_ADDR 0x300F0000
21 #define AIPS1_BASE_ADDR 0x301F0000
22 #define GPIO1_BASE_ADDR 0X30200000
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx7.h100 FSL_IMX7_MMDC_ADDR = 0x80000000,
103 FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000,
106 FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000,
109 FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000,
113 FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
116 FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
117 FSL_IMX7_DMA_APBH_SIZE = 0x8000,
120 FSL_IMX7_GPV6_ADDR = 0x32600000,
121 FSL_IMX7_GPV5_ADDR = 0x32500000,
122 FSL_IMX7_GPV4_ADDR = 0x32400000,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe330000 0x10000>;
220 #clock-cells = <0>;
227 interrupts = <0 48 4>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]

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