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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dintel,keembay-ocs-ecc.yaml44 reg = <0x30001000 0x1000>;
/openbmc/u-boot/configs/
H A DT1040D4RDB_NAND_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
39 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
40 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
51 CONFIG_SF_DEFAULT_MODE=0
H A DT1040D4RDB_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
39 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
40 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
50 CONFIG_SF_DEFAULT_MODE=0
H A DT1040RDB_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
39 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
40 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
51 CONFIG_SF_DEFAULT_MODE=0
H A DT1040D4RDB_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
40 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
41 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
51 CONFIG_SF_DEFAULT_MODE=0
H A DT1040RDB_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
40 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
41 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
52 CONFIG_SF_DEFAULT_MODE=0
H A DT1040RDB_NAND_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
39 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
40 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
52 CONFIG_SF_DEFAULT_MODE=0
H A DT1023RDB_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
41 …;fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel)…
51 CONFIG_SF_DEFAULT_MODE=0
H A DT1023RDB_NAND_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
41 …;fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel)…
52 CONFIG_SF_DEFAULT_MODE=0
H A DT1023RDB_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
42 …;fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel)…
52 CONFIG_SF_DEFAULT_MODE=0
H A DT1024RDB_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
42 …;fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel)…
53 CONFIG_SF_DEFAULT_MODE=0
H A DT1042RDB_PI_NAND_SECURE_BOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
16 CONFIG_BOOTDELAY=0
44 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
45 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
57 CONFIG_SF_DEFAULT_MODE=0
H A DT1042D4RDB_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
41 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
42 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
52 CONFIG_SF_DEFAULT_MODE=0
H A DT1042D4RDB_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
40 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
41 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
51 CONFIG_SF_DEFAULT_MODE=0
H A DT1042RDB_PI_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
41 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
42 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
53 CONFIG_SF_DEFAULT_MODE=0
H A DT1042D4RDB_NAND_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
40 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
41 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
52 CONFIG_SF_DEFAULT_MODE=0
H A DT1042RDB_PI_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
42 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
43 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
54 CONFIG_SF_DEFAULT_MODE=0
H A DT1042RDB_PI_NAND_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
41 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
42 …;fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel)…
54 CONFIG_SF_DEFAULT_MODE=0
H A DT1024RDB_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
43 …;fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel)…
54 CONFIG_SF_DEFAULT_MODE=0
H A DT1024RDB_NAND_defconfig2 CONFIG_SYS_TEXT_BASE=0x30001000
42 …;fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel)…
54 CONFIG_SF_DEFAULT_MODE=0
/openbmc/linux/drivers/usb/chipidea/
H A Dusbmisc_imx.c16 #define MX25_USB_PHY_CTRL_OFFSET 0x08
19 #define MX25_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
20 #define MX25_EHCI_INTERFACE_DIFF_UNI (0 << 0)
21 #define MX25_EHCI_INTERFACE_MASK (0xf)
24 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
30 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
43 #define MX53_USB_OTG_PHY_CTRL_0_OFFSET 0x08
44 #define MX53_USB_OTG_PHY_CTRL_1_OFFSET 0x0c
45 #define MX53_USB_CTRL_1_OFFSET 0x10
46 #define MX53_USB_CTRL_1_H2_XCVR_CLK_SEL_MASK (0x11 << 2)
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7.dtsi61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
109 opp-supported-hw = <0xFF 0x01>;
119 opp-supported-hw = <0xFF 0x02>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]