/openbmc/linux/drivers/pinctrl/starfive/ |
H A D | pinctrl-starfive-jh7110-sys.c | 32 #define JH7110_SYS_GC_BASE 0 37 #define JH7110_SYS_DOEN 0x000 38 #define JH7110_SYS_DOUT 0x040 39 #define JH7110_SYS_GPI 0x080 40 #define JH7110_SYS_GPIOIN 0x118 42 #define JH7110_SYS_GPIOEN 0x0dc 43 #define JH7110_SYS_GPIOIS0 0x0e0 44 #define JH7110_SYS_GPIOIS1 0x0e4 45 #define JH7110_SYS_GPIOIC0 0x0e8 46 #define JH7110_SYS_GPIOIC1 0x0ec [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt8135-apmixedsys.c | 38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0), 39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), 40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2… 41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23… 42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, … 43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0), 44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0), 45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), 46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), 47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), [all …]
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/openbmc/qemu/linux-user/riscv/ |
H A D | vdso-asmoffset.h | 2 # define sizeof_rt_sigframe 0x2b0 3 # define offsetof_uc_mcontext 0x120 4 # define offsetof_freg0 0x80 6 # define sizeof_rt_sigframe 0x340 7 # define offsetof_uc_mcontext 0x130 8 # define offsetof_freg0 0x100
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/openbmc/linux/drivers/tty/serial/8250/ |
H A D | 8250_fourport.c | 16 SERIAL8250_FOURPORT(0x1a0, 9), 17 SERIAL8250_FOURPORT(0x1a8, 9), 18 SERIAL8250_FOURPORT(0x1b0, 9), 19 SERIAL8250_FOURPORT(0x1b8, 9), 20 SERIAL8250_FOURPORT(0x2a0, 5), 21 SERIAL8250_FOURPORT(0x2a8, 5), 22 SERIAL8250_FOURPORT(0x2b0, 5), 23 SERIAL8250_FOURPORT(0x2b8, 5),
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/openbmc/linux/Documentation/devicetree/bindings/display/msm/ |
H A D | dsi-phy-20nm.yaml | 53 reg = <0xfd922a00 0xd4>, 54 <0xfd922b00 0x2b0>, 55 <0xfd922d80 0x7b>; 61 #phy-cells = <0>;
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H A D | dsi-phy-28nm.yaml | 58 reg = <0xfd922a00 0xd4>, 59 <0xfd922b00 0x2b0>, 60 <0xfd922d80 0x7b>; 66 #phy-cells = <0>;
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcie-qhp.h | 10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | nxp,s32g2-siul2-pinctrl.yaml | 17 SIUL2_0 @ 0x4009c000 18 SIUL2_1 @ 0x44010000 41 - description: MSCR registers group 0 in SIUL2_0 44 - description: IMCR registers group 0 in SIUL2_0 54 '-grp[0-9]$': 97 reg = <0x4009c240 0x198>, 99 <0x44010400 0x2c>, 101 <0x44010480 0xbc>, 103 <0x4009ca40 0x150>, 105 <0x44010c1c 0x45c>, [all …]
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/openbmc/linux/tools/perf/arch/powerpc/util/ |
H A D | book3s_hcalls.h | 9 {0x4, "H_REMOVE"}, \ 10 {0x8, "H_ENTER"}, \ 11 {0xc, "H_READ"}, \ 12 {0x10, "H_CLEAR_MOD"}, \ 13 {0x14, "H_CLEAR_REF"}, \ 14 {0x18, "H_PROTECT"}, \ 15 {0x1c, "H_GET_TCE"}, \ 16 {0x20, "H_PUT_TCE"}, \ 17 {0x24, "H_SET_SPRG0"}, \ 18 {0x28, "H_SET_DABR"}, \ [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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/openbmc/u-boot/include/dt-bindings/pinctrl/ |
H A D | pins-imx8mq.h | 24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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/openbmc/linux/Documentation/staging/ |
H A D | static-keys.rst | 233 ffffffff81044294: e9 00 00 00 00 jmpq ffffffff81044299 <sys_getppid+0x9> 234 ffffffff81044299: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax 236 ffffffff810442a2: 48 8b 80 80 02 00 00 mov 0x280(%rax),%rax 237 ffffffff810442a9: 48 8b 80 b0 02 00 00 mov 0x2b0(%rax),%rax 238 ffffffff810442b0: 48 8b b8 e8 02 00 00 mov 0x2e8(%rax),%rdi 243 ffffffff810442c0: 48 c7 c7 e3 54 98 81 mov $0xffffffff819854e3,%rdi 246 ffffffff810442ce: eb c9 jmp ffffffff81044299 <sys_getppid+0x9> 251 …ffffffff810441f0: 8b 05 8a 52 d8 00 mov 0xd8528a(%rip),%eax # ffffffff81dc94… 255 ffffffff810441fc: 75 27 jne ffffffff81044225 <sys_getppid+0x35> 256 ffffffff810441fe: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx6sl-pinfunc.h | 17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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/openbmc/linux/arch/sh/include/mach-sdk7786/mach/ |
H A D | fpga.h | 9 #define SRSTR 0x000 10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */ 12 #define INTASR 0x010 13 #define INTAMR 0x020 14 #define MODSWR 0x030 15 #define INTTESTR 0x040 16 #define SYSSR 0x050 17 #define NRGPR 0x060 19 #define NMISR 0x070 20 #define NMISR_MAN_NMI BIT(0) [all …]
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/openbmc/linux/drivers/gpu/drm/rockchip/ |
H A D | rk3066_hdmi.h | 10 #define GRF_SOC_CON0 0x150 13 #define DDC_SEGMENT_ADDR 0x30 15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11 17 #define N_32K 0x1000 18 #define N_441K 0x1880 19 #define N_882K 0x3100 20 #define N_1764K 0x6200 21 #define N_48K 0x1800 22 #define N_96K 0x3000 23 #define N_192K 0x6000 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/ |
H A D | regs-digctl.h | 15 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ 16 mxs_reg_32(hw_digctl_status) /* 0x010 */ 17 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ 18 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ 19 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ 20 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ 21 uint32_t hw_digctl_writeonce; /* 0x060 */ 23 mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ 24 mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ 25 uint32_t hw_digctl_entropy; /* 0x090 */ [all …]
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/openbmc/u-boot/drivers/ddr/marvell/axp/ |
H A D | xor_regs.h | 11 * to channels 0 & 1 of unit 1 16 #define MV_XOR_REGS_OFFSET(unit) (0x60900) 21 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) 22 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) 25 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30) 26 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40) 27 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50) 28 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60) 31 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) 32 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) [all …]
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/openbmc/u-boot/board/freescale/mx6sllevk/ |
H A D | plugin.S | 11 ldr r1, =0x00080000 12 str r1, [r0, #0x550] 13 ldr r1, =0x00000000 14 str r1, [r0, #0x534] 15 ldr r1, =0x00000030 16 str r1, [r0, #0x2AC] 17 str r1, [r0, #0x548] 18 str r1, [r0, #0x52C] 19 ldr r1, =0x00020000 20 str r1, [r0, #0x530] [all …]
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/openbmc/linux/drivers/media/pci/tw68/ |
H A D | tw68-reg.h | 23 #define TW68_DMAC 0x000 24 #define TW68_DMAP_SA 0x004 25 #define TW68_DMAP_EXE 0x008 26 #define TW68_DMAP_PP 0x00c 27 #define TW68_VBIC 0x010 28 #define TW68_SBUSC 0x014 29 #define TW68_SBUSSD 0x018 30 #define TW68_INTSTAT 0x01C 31 #define TW68_INTMASK 0x020 32 #define TW68_GPIOC 0x024 [all …]
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/openbmc/u-boot/drivers/net/ |
H A D | pic32_eth.h | 14 struct pic32_reg_atomic con1; /* 0x00 */ 15 struct pic32_reg_atomic con2; /* 0x10 */ 16 struct pic32_reg_atomic txst; /* 0x20 */ 17 struct pic32_reg_atomic rxst; /* 0x30 */ 18 struct pic32_reg_atomic ht0; /* 0x40 */ 19 struct pic32_reg_atomic ht1; /* 0x50 */ 20 struct pic32_reg_atomic pmm0; /* 0x60 */ 21 struct pic32_reg_atomic pmm1; /* 0x70 */ 22 struct pic32_reg_atomic pmcs; /* 0x80 */ 23 struct pic32_reg_atomic pmo; /* 0x90 */ [all …]
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/openbmc/u-boot/board/atmel/sama5d4ek/ |
H A D | sama5d4ek.c | 46 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ in sama5d4ek_nand_hw_init() 47 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ in sama5d4ek_nand_hw_init() 48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ in sama5d4ek_nand_hw_init() 49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ in sama5d4ek_nand_hw_init() 50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ in sama5d4ek_nand_hw_init() 51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ in sama5d4ek_nand_hw_init() 52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ in sama5d4ek_nand_hw_init() 53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ in sama5d4ek_nand_hw_init() 54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ in sama5d4ek_nand_hw_init() 55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ in sama5d4ek_nand_hw_init() [all …]
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