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123

/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6348.dtsi20 reg = <0xfffe0000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
41 #clock-cells = <0>;
48 reg = <0xfffe0004 0x4>;
55 reg = <0x1fc00000 0x2000000>;
71 reg = <0xfffe0008 0x4>;
77 offset = <0x0>;
78 mask = <0x1>;
[all …]
H A Dbrcm,bcm6358.dtsi20 reg = <0xfffe0000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
48 #clock-cells = <0>;
55 reg = <0xfffe0004 0x4>;
62 reg = <0x1e000000 0x2000000>;
78 reg = <0xfffe0008 0x4>;
84 offset = <0x0>;
85 mask = <0x1>;
[all …]
H A Dbrcm,bcm6338.dtsi20 reg = <0xfffe0000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
41 #clock-cells = <0>;
48 reg = <0xfffe0004 0x4>;
55 reg = <0x1fc00000 0x400000>;
71 reg = <0xfffe0008 0x4>;
77 offset = <0x0>;
78 mask = <0x1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmmc_host_def.h31 #define T2_BASE 0x48002000
34 unsigned char res1[0x274]; /* 0x000 */
35 unsigned int devconf0; /* 0x274 */
36 unsigned char res2[0x060]; /* 0x278 */
37 unsigned int devconf1; /* 0x2D8 */
38 unsigned char res3[0x16C]; /* 0x2DC */
39 unsigned int ctl_prog_io1; /* 0x448 */
40 unsigned char res4[0x0D4]; /* 0x44C */
41 unsigned int pbias_lite; /* 0x520 */
55 #define PBIASLITEVMODE0 (1 << 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imxrt1050.yaml72 reg = <0x401f8000 0x4000>;
76 <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
77 <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
/openbmc/linux/drivers/crypto/intel/qat/qat_4xxx/
H A Dadf_4xxx_hw_data.h10 #define ADF_4XXX_SRAM_BAR 0
14 #define ADF_4XXX_TX_RINGS_MASK 0x1
17 #define ADF_4XXX_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
20 #define ADF_4XXX_FUSECTL0_OFFSET (0x2C8)
21 #define ADF_4XXX_FUSECTL1_OFFSET (0x2CC)
22 #define ADF_4XXX_FUSECTL2_OFFSET (0x2D0)
23 #define ADF_4XXX_FUSECTL3_OFFSET (0x2D4)
24 #define ADF_4XXX_FUSECTL4_OFFSET (0x2D8)
25 #define ADF_4XXX_FUSECTL5_OFFSET (0x2DC)
27 #define ADF_4XXX_ACCELERATORS_MASK (0x1)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Daccel.h14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx53-pinfunc.h13 #define IMX_PAD_SION 0x40000000
18 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
19 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
20 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
21 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
22 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
23 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
24 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
25 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
26 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v5_5nm.h10 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
11 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
12 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
13 #define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c
14 #define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10
15 #define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x14
16 #define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x18
17 #define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c
18 #define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x20
19 #define QSERDES_V5_5NM_TX_LPB_EN 0x24
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8173-apmixedsys.c17 #define REGOFF_REF2USB 0x8
18 #define REGOFF_HDMI_REF 0x40
52 { .div = 0, .freq = MT8173_PLL_FMAX },
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
62 21, 0x204, 24, 0x0, 0x204, 0),
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
64 21, 0x214, 24, 0x0, 0x214, 0),
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
66 0x220, 4, 0x0, 0x224, 0),
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dti816x_emif4.c29 writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
30 writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
31 writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
32 writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
37 writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ in ddr_init_settings()
38 writel(0x1, DDRPHY_CONFIG_BASE + 0x104); in ddr_init_settings()
39 writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); in ddr_init_settings()
40 writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); in ddr_init_settings()
41 writel(0x1, DDRPHY_CONFIG_BASE + 0x240); in ddr_init_settings()
42 writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); in ddr_init_settings()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dmux_dra7xx.h14 #define PULL_ENA (0 << 16)
21 #define PIN_OUTPUT (0 | PULL_DIS)
23 #define PIN_OUTPUT_PULLDOWN (0)
29 #define M0 0
51 #define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
52 #define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
53 #define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
54 #define VIRTUAL_MODE3 (MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
55 #define VIRTUAL_MODE4 (MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
56 #define VIRTUAL_MODE5 (MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
[all …]
/openbmc/linux/drivers/clk/st/
H A Dclkgen-pll.c26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
77 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
78 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpins-imx8mq.h24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfec_mpc52xx.h34 u32 fec_id; /* FEC + 0x000 */
35 u32 ievent; /* FEC + 0x004 */
36 u32 imask; /* FEC + 0x008 */
38 u32 reserved0[1]; /* FEC + 0x00C */
39 u32 r_des_active; /* FEC + 0x010 */
40 u32 x_des_active; /* FEC + 0x014 */
41 u32 r_des_active_cl; /* FEC + 0x018 */
42 u32 x_des_active_cl; /* FEC + 0x01C */
43 u32 ivent_set; /* FEC + 0x020 */
44 u32 ecntrl; /* FEC + 0x024 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Diomux-mx53.h30 MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
31 MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
32 MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
33 MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
34 MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
35 MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
36 MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
37 MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
38 MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
39 MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
[all …]

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