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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-mss-pil.yaml216 reg = <0x04080000 0x10000>, <0x04180000 0x48>;
219 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
221 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
224 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
248 qcom,smem-states = <&modem_smp2p_out 0>;
255 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
256 qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
257 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sm6350.c35 .offset = 0x0,
38 .enable_reg = 0x52010,
39 .enable_mask = BIT(0),
52 { 0x1, 2 },
57 .offset = 0x0,
74 { 0x3, 3 },
79 .offset = 0x0,
96 .offset = 0x6000,
99 .enable_reg = 0x52010,
113 { 0x1, 2 },
[all …]
H A Dgcc-sdm660.c51 .offset = 0x0,
54 .enable_reg = 0x52000,
55 .enable_mask = BIT(0),
81 .offset = 0x00000,
94 .offset = 0x1000,
97 .enable_reg = 0x52000,
124 .offset = 0x1000,
137 .offset = 0x77000,
140 .enable_reg = 0x52000,
154 .offset = 0x77000,
[all …]
H A Dgcc-sm8450.c40 .offset = 0x0,
43 .enable_reg = 0x62018,
44 .enable_mask = BIT(0),
57 { 0x1, 2 },
62 .offset = 0x0,
79 .offset = 0x4000,
82 .enable_reg = 0x62018,
96 .offset = 0x9000,
99 .enable_reg = 0x62018,
113 { P_BI_TCXO, 0 },
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-mdm9607.c37 .offset = 0x21000,
40 .enable_reg = 0x45000,
41 .enable_mask = BIT(0),
55 .offset = 0x21000,
67 { P_XO, 0 },
77 .l_reg = 0x20004,
78 .m_reg = 0x20008,
79 .n_reg = 0x2000c,
80 .config_reg = 0x20010,
81 .mode_reg = 0x20000,
[all …]
H A Dgcc-sdm845.c38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x76000,
58 .enable_reg = 0x52000,
72 .offset = 0x13000,
75 .enable_reg = 0x52000,
89 { 0x0, 1 },
90 { 0x1, 2 },
91 { 0x3, 4 },
[all …]
H A Dgcc-sc7180.c36 .offset = 0x0,
39 .enable_reg = 0x52010,
40 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
89 .offset = 0x01000,
92 .enable_reg = 0x52010,
107 .offset = 0x76000,
110 .enable_reg = 0x52010,
125 .offset = 0x13000,
[all …]
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-sc7280.c44 .offset = 0x0,
47 .enable_reg = 0x52010,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 { 0x3, 3 },
88 .offset = 0x0,
105 .offset = 0x1000,
108 .enable_reg = 0x52010,
122 .offset = 0x1e000,
[all …]
H A Dgcc-sm8550.c56 .offset = 0x0,
59 .enable_reg = 0x52018,
60 .enable_mask = BIT(0),
73 { 0x1, 2 },
78 .offset = 0x0,
95 .offset = 0x4000,
98 .enable_reg = 0x52018,
112 .offset = 0x7000,
115 .enable_reg = 0x52018,
129 .offset = 0x9000,
[all …]
H A Dgcc-ipq5018.c61 .offset = 0x21000,
64 .enable_reg = 0x0b000,
65 .enable_mask = BIT(0),
76 .offset = 0x4a000,
79 .enable_reg = 0x0b000,
91 .offset = 0x24000,
94 .enable_reg = 0x0b000,
106 .offset = 0x25000,
109 .enable_reg = 0x0b000,
121 .offset = 0x21000,
[all …]
H A Dgcc-sm8350.c44 .offset = 0x0,
47 .enable_reg = 0x52018,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 .offset = 0x76000,
86 .enable_reg = 0x52018,
101 .offset = 0x1c000,
104 .enable_reg = 0x52018,
119 { P_BI_TCXO, 0 },
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
H A Dgcc-ipq6018.c50 .offset = 0x21000,
53 .enable_reg = 0x0b000,
54 .enable_mask = BIT(0),
79 .offset = 0x21000,
98 { P_XO, 0 },
104 .offset = 0x25000,
108 .enable_reg = 0x0b000,
122 .offset = 0x25000,
136 .offset = 0x37000,
139 .enable_reg = 0x0b000,
[all …]
H A Dgcc-ipq8074.c52 .offset = 0x21000,
55 .enable_reg = 0x0b000,
56 .enable_mask = BIT(0),
82 .offset = 0x21000,
95 .offset = 0x4a000,
98 .enable_reg = 0x0b000,
114 .offset = 0x4a000,
127 .offset = 0x24000,
130 .enable_reg = 0x0b000,
146 .offset = 0x24000,
[all …]
H A Dgcc-sc8280xp.c113 .offset = 0x0,
116 .enable_reg = 0x52028,
117 .enable_mask = BIT(0),
128 { 0x1, 2 },
133 .offset = 0x0,
150 .offset = 0x2000,
153 .enable_reg = 0x52028,
165 .offset = 0x76000,
168 .enable_reg = 0x52028,
180 .offset = 0x1a000,
[all …]
/openbmc/linux/drivers/bus/
H A Dti-sysc.c30 #define DIS_SGX BIT(0)
167 writew_relaxed(value & 0xffff, ddata->module_va + offset); in sysc_write()
170 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_write()
191 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_read()
213 if (offset < 0) in sysc_read_revision()
214 return 0; in sysc_read_revision()
223 if (offset < 0) in sysc_read_sysconfig()
224 return 0; in sysc_read_sysconfig()
233 if (offset < 0) in sysc_read_sysstatus()
234 return 0; in sysc_read_sysstatus()
[all …]