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/openbmc/u-boot/configs/
H A Drock_defconfig5 CONFIG_SYS_TEXT_BASE=0x60000000
6 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DEBUG_UART_BASE=0x20064000
12 CONFIG_SPL_STACK_R_ADDR=0x60080000
19 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
31 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks as…
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Drockchip,pinctrl.yaml16 options with option 0 being used as a GPIO.
81 "gpio@[0-9a-f]+$":
101 minimum: 0
124 - minimum: 0
128 - minimum: 0
132 - minimum: 0
135 Mux 0 means GPIO and mux 1 to N means
156 reg = <0x20034000 0x100>;
181 reg = <0x20064000 0x400>;
184 pinctrl-0 = <&uart2_xfer>;
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt6 muxing options with option 0 being the use as a GPIO.
61 The MUX 0 means gpio and MUX 1 to N mean the specific device function.
81 reg = <0x20034000 0x100>;
108 reg = <0x20064000 0x400>;
116 pinctrl-0 = <&uart2_xfer>;
129 gpio0: gpio0@0x2000a000 {
131 reg = <0x2000a000 0x100>;
142 gpio1: gpio1@0x2003c000 {
144 reg = <0x2003c000 0x100>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi40 reg = <0x20018000 0x4000>;
41 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
51 reg = <0x2001c000 0x4000>;
52 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
63 reg = <0x20078000 0x4000>;
76 #clock-cells = <0>;
82 reg = <0x10138000 0x1000>;
89 reg = <0x1013c000 0x100>;
94 reg = <0x1013c200 0x20>;
95 interrupts = <GIC_PPI 11 0x304>;
[all …]
H A Drk3036.dtsi29 reg = <0x60000000 0x40000000>;
41 #size-cells = <0>;
47 reg = <0xf00>;
60 reg = <0xf01>;
73 reg = <0x20078000 0x4000>;
75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
87 #clock-cells = <0>;
102 reg = <0x20000000 0x1000>;
112 reg = <0x20060000 0x100>;
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
[all …]
H A Drk3128.dtsi39 reg = <0x60000000 0x40000000>;
52 #size-cells = <0>;
55 cpu0:cpu@0x000 {
58 reg = <0x000>;
68 cpu1:cpu@0x001 {
71 reg = <0x001>;
74 cpu2:cpu@0x002 {
77 reg = <0x002>;
80 cpu3:cpu@0x003 {
83 reg = <0x003>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi35 #clock-cells = <0>;
41 reg = <0x10090000 0x10000>;
52 reg = <0x10104000 0x800>;
64 reg = <0x10138000 0x1000>;
71 reg = <0x1013c000 0x100>;
76 reg = <0x1013c200 0x20>;
90 reg = <0x1013c600 0x20>;
99 reg = <0x1013d000 0x1000>,
100 <0x1013c100 0x0100>;
105 reg = <0x10124000 0x400>;
[all …]
H A Drk3036.dtsi34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
[all …]
H A Drk3128.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
47 reg = <0xf01>;
53 reg = <0xf02>;
59 reg = <0xf03>;
77 #clock-cells = <0>;
82 reg = <0x100a0000 0x1000>;
87 reg = <0x10139000 0x1000>,
88 <0x1013a000 0x1000>,
89 <0x1013c000 0x2000>,
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]