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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt6 muxing options with option 0 being the use as a GPIO.
61 The MUX 0 means gpio and MUX 1 to N mean the specific device function.
81 reg = <0x20034000 0x100>;
108 reg = <0x20064000 0x400>;
116 pinctrl-0 = <&uart2_xfer>;
129 gpio0: gpio0@0x2000a000 {
131 reg = <0x2000a000 0x100>;
142 gpio1: gpio1@0x2003c000 {
144 reg = <0x2003c000 0x100>;
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Drockchip,gpio-bank.yaml66 reg = <0x2000a000 0x100>;
79 reg = <0x2003c000 0x100>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3188.dtsi17 #size-cells = <0>;
20 cpu0: cpu@0 {
24 reg = <0x0>;
43 reg = <0x1>;
49 reg = <0x2>;
55 reg = <0x3>;
61 reg = <0x10080000 0x8000>;
64 ranges = <0 0x10080000 0x8000>;
66 smp-sram@0 {
68 reg = <0x0 0x50>;
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c19 #define CRU_BASE 0x20000000
20 #define GRF_BASE 0x20008000
21 #define DDR_PHY_BASE 0x2000a000
22 #define DDR_PCTL_BASE 0x20004000
23 #define CPU_AXI_BUS_BASE 0x10128000
43 const struct rk3036_ddr_timing ddr_timing = {0x18c,
44 {0x18c, 0xc8, 0x1f4, 0x27, 0x4e,
45 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04,
46 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03,
47 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0},
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
42 reg = <0x1>;
53 reg = <0x10080000 0x10000>;
56 ranges = <0 0x10080000 0x10000>;
58 smp-sram@0 {
60 reg = <0x0 0x50>;
66 reg = <0x1010c000 0x19c>;
81 #size-cells = <0>;
[all …]
H A Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
35 reg = <0x1>;
43 reg = <0x2>;
51 reg = <0x3>;
57 cpu0_opp_table: opp-table-0 {
104 reg = <0x10080000 0x8000>;
107 ranges = <0 0x10080000 0x8000>;
109 smp-sram@0 {
[all …]
/openbmc/linux/arch/m68k/ifpsp060/src/
H A Ditest.S51 align 0x4
58 addq.l &0x4,%sp
63 addq.l &0x4,%sp
67 addq.l &0x4,%sp
74 movm.l &0x3f3c,-(%sp)
78 addq.l &0x4,%sp
84 addq.l &0x4,%sp
94 addq.l &0x4,%sp
104 addq.l &0x4,%sp
114 addq.l &0x4,%sp
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1)
63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
64 … | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0
120 #define ASTMMC_INIT_VER 0x12 @ 8bit verison number
121 #define ASTMMC_INIT_DATE 0x20171027 @ Release date
133 //#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving
134 //#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving
157 #define ASTMMC_REGIDX_010 0x00
158 #define ASTMMC_REGIDX_014 0x04
159 #define ASTMMC_REGIDX_018 0x08
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S41 * 1. Change init value of MCR18[4] from '1' to '0'
46 * EC2. Modify DLL1 MAdj = 0x4C
52 * EC1. Set for wide screen supporting, 0x1e6e2040[0] = 1
55 * EC1. Clear MCR04[10] = 0 before doing DRAM initial
56 * EC2. Add USB2.0 port initial
59 * EC1. Modify DDR driving on MCR6C from 0x2312 to 0x2323
60 * EC2. Reset RNG to fix RNG read 0 issue
71 …* // when enabled, must define the ECC protected memory size at 0x1e6e00…
93 .word 0xff00ff00
94 .word 0xcc33cc33
[all …]