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/openbmc/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
H A D03325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
74 do_test $align "write -P 0xa 0x200 0x400" "$TEST_IMG" | _filter_qemu_io
75 do_test $align "write -P 0xa 0x20000 0x600" "$TEST_IMG" | _filter_qemu_io
76 do_test $align "$write_zero_cmd 0x400 0x20000" "$TEST_IMG" | _filter_qemu_io
80 do_test $align "read -P 0xa 0x200 0x200" "$TEST_IMG" | _filter_qemu_io
81 do_test $align "read -P 0x0 0x400 0x20000" "$TEST_IMG" | _filter_qemu_io
82 do_test $align "read -P 0xa 0x20400 0x200" "$TEST_IMG" | _filter_qemu_io
86 do_test $align "write -P 0xb 0x10000 0x10000" "$TEST_IMG" | _filter_qemu_io
87 do_test $align "$write_zero_cmd 0x10000 0x10000" "$TEST_IMG" | _filter_qemu_io
[all …]
H A D176.out3 === Test pass snapshot.0 ===
30 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
32 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
33 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
34 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
36 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
37 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
38 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
70 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
72 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
[all …]
H A D097.out3 === Test pass 0 ===
30 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
32 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
33 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
34 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
36 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
37 0x7ffe0000 0x20000 TEST_DIR/t.IMGFMT.itmd
38 0x83400000 0x200 TEST_DIR/t.IMGFMT.itmd
67 0x7ffd0000 0x30000 TEST_DIR/t.IMGFMT.base
69 0x7ffd0000 0x10000 TEST_DIR/t.IMGFMT.base
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dstv090x_reg.h13 #define STV090x_MID 0xf100
16 #define STV090x_OFFST_MRELEASE_FIELD 0
19 #define STV090x_DACR1 0xf113
22 #define STV090x_OFFST_DACR1_VALUE_FIELD 0
25 #define STV090x_DACR2 0xf114
26 #define STV090x_OFFST_DACR2_VALUE_FIELD 0
29 #define STV090x_OUTCFG 0xf11c
39 #define STV090x_MODECFG 0xf11d
41 #define STV090x_IRQSTATUS3 0xf120
52 #define STV090x_OFFST_SDVBS1_PRF_1_FIELD 0
[all …]
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output()
25 u32 tmp = 0; in medusa_enable_bluefield_output()
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
H A Dlan966x.dtsi27 #size-cells = <0>;
29 cpu@0 {
33 reg = <0x0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
90 reg = <0x00200000 0x80000>,
91 <0xe0808000 0x400>;
[all …]
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
46 reg = <0x740000 0x1000>;
62 reg = <0x73c000 0x1000>;
78 reg = <0x20000000 0x20000000>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
90 #clock-cells = <0>;
[all …]
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
88 hysteresis = <0>;
94 hysteresis = <0>;
100 hysteresis = <0>;
122 #clock-cells = <0>;
127 #clock-cells = <0>;
132 #clock-cells = <0>;
151 reg = <0x100000 0x20000>;
[all …]
H A Dat91sam9260.dtsi41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x04000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 reg = <0x002ff000 0x2000>;
[all …]
H A Dat91sam9261.dtsi38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
[all …]
/openbmc/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi11 reg = <0x00 0x70000000 0x00 0x800000>;
14 ranges = <0x00 0x00 0x70000000 0x800000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
21 reg = <0x1f0000 0x10000>;
25 reg = <0x200000 0x200000>;
36 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
37 <0x00 0x01900000 0x00 0x100000>, /* GICR */
38 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
39 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
/openbmc/linux/drivers/pmdomain/renesas/
H A Dr8a774a1-sysc.c17 { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON,
20 { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
22 { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
24 { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON,
26 { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
28 { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
30 { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
32 { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
34 { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON },
[all …]
H A Dr8a774e1-sysc.c17 { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
19 { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
20 { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
21 { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
22 { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
23 { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
24 { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
25 { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
26 { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
[all …]
H A Dr8a7796-sysc.c17 { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
20 { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU,
22 { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU,
24 { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON,
26 { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU,
28 { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU,
30 { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU,
32 { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU,
34 { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON },
[all …]
H A Dr8a77980-sysc.c17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON,
30 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
31 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
32 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
[all …]
/openbmc/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier-mio.c35 .reg = 0x30 + 0x200 * (ch), \
37 0x00031000, \
38 0x00031000, \
39 0x00031000, \
40 0x00031000, \
41 0x00001300, \
42 0x00001300, \
43 0x00001300, \
44 0x00001300, \
47 0x00000000, \
[all …]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra124.c16 .id = 0x00,
21 .reg = 0x34c,
22 .shift = 0,
23 .mask = 0xff,
24 .def = 0x0,
28 .id = 0x01,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
39 .mask = 0xff,
[all …]
H A Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
32 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Drcar-gen3-thermal.yaml107 reg = <0xe6198000 0x100>,
108 <0xe61a0000 0x100>,
109 <0xe61a8000 0x100>;
123 thermal-sensors = <&tsc 0>;
141 reg = <0xe6190000 0x200>,
142 <0xe6198000 0x200>,
143 <0xe61a0000 0x200>,
144 <0xe61a8000 0x200>,
145 <0xe61b0000 0x200>;
/openbmc/u-boot/include/environment/ti/
H A Ddfu.h13 "boot part 0 1;" \
14 "rootfs part 0 2;" \
15 "MLO fat 0 1;" \
16 "MLO.raw raw 0x100 0x100;" \
17 "u-boot.img.raw raw 0x300 0x1000;" \
18 "u-env.raw raw 0x1300 0x200;" \
19 "spl-os-args.raw raw 0x1500 0x200;" \
20 "spl-os-image.raw raw 0x1700 0x6900;" \
21 "spl-os-args fat 0 1;" \
22 "spl-os-image fat 0 1;" \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]

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