Searched +full:0 +full:x1ff80 (Results 1 – 8 of 8) sorted by relevance
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | smu8.h | 65 #define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80 66 #define SMU8_UNBCSR_START_ADDR 0xC0100000 68 #define SMN_MP1_SRAM_START_ADDR 0x10000000
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/openbmc/linux/Documentation/devicetree/bindings/sram/ |
H A D | sram.yaml | 159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 163 ranges = <0 0x5c000000 0x40000>; 166 reg = <0x100 0x50>; 170 reg = <0x1000 0x1000>; 175 reg = <0x20000 0x20000>; 190 reg = <0x02020000 0x54000>; 193 ranges = <0 0x02020000 0x54000>; 195 smp-sram@0 { 197 reg = <0x0 0x1000>; 202 reg = <0x53000 0x1000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/amlogic/ |
H A D | meson8b.dtsi | 19 #size-cells = <0>; 25 reg = <0x200>; 37 reg = <0x201>; 49 reg = <0x202>; 61 reg = <0x203>; 169 hwrom@0 { 170 reg = <0x0 0x200000>; 225 reg = <0xc8000000 0x8000>; 228 ranges = <0x0 0xc8000000 0x8000>; 232 reg = <0x400 0x20>; [all …]
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H A D | meson8.dtsi | 21 #size-cells = <0>; 27 reg = <0x200>; 39 reg = <0x201>; 51 reg = <0x202>; 63 reg = <0x203>; 177 hwrom@0 { 178 reg = <0x0 0x200000>; 193 reg = <0x4f00000 0x100000>; 248 reg = <0xc8000000 0x8000>; 251 ranges = <0x0 0xc8000000 0x8000>; [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_7_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]
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H A D | gmc_8_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]
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/openbmc/linux/drivers/scsi/qla2xxx/ |
H A D | qla_sup.c | 35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access() 39 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access() 42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access() 60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); in qla2x00_unlock_nvram_access() 98 * Bit 15-0 = write data 107 uint16_t data = 0; in qla2x00_nvram_request() 112 for (cnt = 0; cnt < 11; cnt++) { in qla2x00_nvram_request() 116 qla2x00_nv_write(ha, 0); in qla2x00_nvram_request() 121 for (cnt = 0; cnt < 16; cnt++) { in qla2x00_nvram_request() 194 qla2x00_nv_write(ha, 0); in qla2x00_write_nvram_word() [all …]
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/openbmc/qemu/target/xtensa/core-test_kc705_be/ |
H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 }, 32 { "LEND", 1, 0 }, 33 { "LCOUNT", 2, 0 }, 34 { "BR", 4, 0 }, 35 { "ACCLO", 16, 0 }, 36 { "ACCHI", 17, 0 }, 37 { "M0", 32, 0 }, 38 { "M1", 33, 0 }, 39 { "M2", 34, 0 }, 40 { "M3", 35, 0 }, [all …]
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