/openbmc/linux/drivers/staging/wlan-ng/ |
H A D | p80211metadef.h | 35 P80211DID_MKITEM(1) | 0x00000000) 39 P80211DID_MKITEM(2) | 0x00000000) 46 P80211DID_MKITEM(1) | 0x00000000) 50 P80211DID_MKITEM(2) | 0x00000000) 87 P80211DID_MKITEM(1) | 0x00000000) 91 P80211DID_MKITEM(2) | 0x00000000) 98 P80211DID_MKITEM(1) | 0x00000000) 102 P80211DID_MKITEM(2) | 0x00000000) 106 P80211DID_MKITEM(3) | 0x00000000) 113 P80211DID_MKITEM(1) | 0x00000000) [all …]
|
/openbmc/linux/arch/arm/boot/dts/realtek/ |
H A D | rtd1195.dtsi | 6 /memreserve/ 0x00000000 0x0000a800; /* boot code */ 7 /memreserve/ 0x0000a800 0x000f5800; 8 /memreserve/ 0x17fff000 0x00001000; 21 #size-cells = <0>; 23 cpu0: cpu@0 { 26 reg = <0x0>; 33 reg = <0x1>; 44 reg = <0x0000b000 0x1000>; 48 reg = <0x01b00000 0x400000>; 52 reg = <0x01ffe000 0x4000>; [all …]
|
/openbmc/u-boot/board/sr1500/qts/ |
H A D | iocsr_config.h | 15 0x00100000, 16 0x40000000, 17 0x0FF00000, 18 0xC0000000, 19 0x0000003F, 20 0x00008000, 21 0x000E0180, 22 0x18060000, 23 0x18000000, 24 0x00018060, [all …]
|
/openbmc/linux/arch/arm64/boot/dts/arm/ |
H A D | vexpress-v2f-1xv7-ca53x2.dts | 20 arm,hbi = <0x247>; 21 arm,vexpress,site = <0xf>; 42 #size-cells = <0>; 44 cpu@0 { 47 reg = <0 0>; 54 reg = <0 1>; 67 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ 75 /* Chipselect 2 is physically at 0x18000000 */ 79 reg = <0 0x18000000 0 0x00800000>; 87 #address-cells = <0>; [all …]
|
/openbmc/u-boot/arch/mips/include/asm/ |
H A D | malta.h | 10 #define MALTA_GT_BASE 0x1be00000 11 #define MALTA_GT_PCIIO_BASE 0x18000000 12 #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) 14 #define MALTA_MSC01_BIU_BASE 0x1bc80000 15 #define MALTA_MSC01_PCI_BASE 0x1bd00000 16 #define MALTA_MSC01_PBC_BASE 0x1bd40000 17 #define MALTA_MSC01_IP1_BASE 0x1bc00000 18 #define MALTA_MSC01_IP1_SIZE 0x00400000 19 #define MALTA_MSC01_IP2_BASE1 0x10000000 20 #define MALTA_MSC01_IP2_SIZE1 0x08000000 [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/bus/ |
H A D | brcm,bus-axi.txt | 26 reg = <0x18000000 0x1000>; 27 ranges = <0x00000000 0x18000000 0x00100000>; 31 interrupt-map-mask = <0x000fffff 0xffff>; 33 /* Ethernet Controller 0 */ 34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 39 /* PCIe Controller 0 */ 40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, [all …]
|
/openbmc/linux/arch/sh/include/mach-common/mach/ |
H A D | sh7785lcr.h | 11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C 14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB 18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 23 #define NOR_FLASH_ADDR 0x00000000 [all …]
|
/openbmc/u-boot/include/configs/ |
H A D | udoo.h | 28 #define CONFIG_DWC_AHSATA_PORT_ID 0 41 #define CONFIG_SYS_MEMTEST_START 0x10000000 45 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 48 "console=ttymxc1,115200\0" \ 49 "fdt_high=0xffffffff\0" \ 50 "initrd_high=0xffffffff\0" \ 51 "fdtfile=undefined\0" \ 52 "fdt_addr=0x18000000\0" \ 53 "fdt_addr_r=0x18000000\0" \ 54 "ip_dyn=yes\0" \ [all …]
|
H A D | el6x_common.h | 28 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 43 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 54 "board="__stringify(CONFIG_BOARD_NAME)"\0" \ 55 "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ 56 "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \ 57 "console=" CONSOLE_DEV "\0" \ 58 "fdtfile=undefined\0" \ 59 "fdt_high=0xffffffff\0" \ 60 "fdt_addr_r=0x18000000\0" \ 61 "fdt_addr=0x18000000\0" \ [all …]
|
H A D | kp_imx6q_tpc.h | 31 #define CONFIG_FEC_MXC_PHYADDR 0 49 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 51 #define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ 65 #define CONFIG_MXC_USB_FLAGS 0 75 #define CONFIG_LOADADDR 0x12000000 80 "console=ttymxc0,115200\0" \ 81 "fdt_addr=0x18000000\0" \ 82 "fdt_high=0xffffffff\0" \ 83 "initrd_high=0xffffffff\0" \ 84 "kernel_addr_r=0x10008000\0" \ [all …]
|
H A D | dh_imx6.h | 17 * 0x00_0000-0x00_ffff ... U-Boot SPL 18 * 0x01_0000-0x0f_ffff ... U-Boot 19 * 0x10_0000-0x10_ffff ... U-Boot env #1 20 * 0x11_0000-0x11_ffff ... U-Boot env #2 21 * 0x12_0000-0x1f_ffff ... UNUSED 26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 48 #define CONFIG_FEC_MXC_PHYADDR 0 66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 73 #define CONFIG_DWC_AHSATA_PORT_ID 0 91 #define CONFIG_MXC_USB_FLAGS 0 [all …]
|
H A D | mx6cuboxi.h | 25 #define CONFIG_DWC_AHSATA_PORT_ID 0 34 #define CONFIG_FEC_MXC_PHYADDR 0 51 #define CONFIG_MXC_USB_FLAGS 0 69 #define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ 73 "som_rev=undefined\0" \ 74 "has_emmc=undefined\0" \ 75 "fdtfile=undefined\0" \ 76 "fdt_addr_r=0x18000000\0" \ 77 "fdt_addr=0x18000000\0" \ 78 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ [all …]
|
H A D | wandboard.h | 27 #define CONFIG_DWC_AHSATA_PORT_ID 0 32 #define CONFIG_SYS_MEMTEST_START 0x10000000 47 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 51 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 56 #define CONFIG_MXC_USB_FLAGS 0 80 "console=ttymxc0\0" \ 81 "splashpos=m,m\0" \ 82 "fdtfile=undefined\0" \ 83 "fdt_high=0xffffffff\0" \ 84 "initrd_high=0xffffffff\0" \ [all …]
|
/openbmc/qemu/tests/tcg/openrisc/ |
H A D | test_logic.c | 8 b = 0x9743; in main() 9 c = 0x2; in main() 10 result = 0x25d0c; in main() 12 ("l.sll %0, %1, %2\n\t" in main() 21 b = 0x9743; in main() 22 result = 0x25d0c; in main() 24 ("l.slli %0, %1, 0x2\n\t" in main() 33 b = 0x7654; in main() 34 c = 0x03; in main() 35 result = 0xeca; in main() [all …]
|
/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | s3c6410-smdk6410.dts | 24 reg = <0x50000000 0x8000000>; 31 fin_pll: oscillator-0 { 35 #clock-cells = <0>; 42 #clock-cells = <0>; 49 reg = <0x18000000 0x8000000>; 54 reg = <0x18000000 0x10000>; 70 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 77 pinctrl-0 = <&uart0_data>, <&uart0_fctl>; 83 pinctrl-0 = <&uart1_data>; 89 pinctrl-0 = <&uart2_data>; [all …]
|
H A D | s3c6410-mini6410.dts | 24 reg = <0x50000000 0x10000000>; 31 fin_pll: oscillator-0 { 35 #clock-cells = <0>; 42 #clock-cells = <0>; 49 reg = <0x18000000 0x8000000>; 54 reg = <0x18000000 0x2>, <0x18000004 0x2>; 64 pinctrl-0 = <&gpio_keys>; 69 gpios = <&gpn 0 GPIO_ACTIVE_LOW>; 127 pinctrl-0 = <&gpio_leds>; 154 pwms = <&pwm 0 1000000 0>; [all …]
|
/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca5s.dts | 16 arm,hbi = <0x225>; 17 arm,vexpress,site = <0xf>; 36 #size-cells = <0>; 38 cpu@0 { 41 reg = <0>; 55 reg = <0x80000000 0x40000000>; 63 /* Chipselect 2 is physically at 0x18000000 */ 67 reg = <0x18000000 0x00800000>; 74 reg = <0x2a110000 0x1000>; 75 interrupts = <0 85 4>; [all …]
|
H A D | vexpress-v2p-ca15-tc1.dts | 16 arm,hbi = <0x237>; 17 arm,vexpress,site = <0xf>; 36 #size-cells = <0>; 38 cpu@0 { 41 reg = <0>; 53 reg = <0 0x80000000 0 0x40000000>; 61 /* Chipselect 2 is physically at 0x18000000 */ 65 reg = <0 0x18000000 0 0x00800000>; 72 reg = <0 0x2b000000 0 0x1000>; 73 interrupts = <0 85 4>; [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/gpu/ |
H A D | nvidia,gk20a.txt | 46 reg = <0x0 0x57000000 0x0 0x01000000>, 47 <0x0 0x58000000 0x0 0x01000000>; 64 reg = <0x0 0x57000000 0x0 0x01000000>, 65 <0x0 0x58000000 0x0 0x01000000>; 82 reg = <0x0 0x17000000 0x0 0x1000000>, 83 <0x0 0x18000000 0x0 0x1000000>; 100 reg = <0x17000000 0x1000000>, 101 <0x18000000 0x1000000>;
|
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
H A D | config.h | 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ 25 #define CONFIG_SYS_PAGE_SIZE 0x10000 31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 48 #define GICD_BASE 0x06000000 49 #define GICR_BASE 0x06100000 52 #define SMMU_BASE 0x05000000 /* GR0 Base */ 69 #define CCI_MN_BASE 0x04000000 [all …]
|
/openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
H A D | rtw8852a_rfk_table.c | 8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001), 9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002), 10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001), 11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002), 12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005), 13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005), 14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005), 15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005), 16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), 17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), [all …]
|
/openbmc/u-boot/board/cadence/xtfpga/ |
H A D | Kconfig | 33 default 0x04000000 if XTFPGA_LX60 34 default 0x03000000 if XTFPGA_LX110 35 default 0x06000000 if XTFPGA_LX200 36 default 0x18000000 if XTFPGA_ML605 37 default 0x38000000 if XTFPGA_KC705
|
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/ |
H A D | soc.h | 9 #define SI_ENUM_BASE_DEFAULT 0x18000000 12 #define SICF_BIST_EN 0x8000 13 #define SICF_PME_EN 0x4000 14 #define SICF_CORE_BITS 0x3ffc 15 #define SICF_FGC 0x0002 16 #define SICF_CLOCK_EN 0x0001 19 #define SISF_BIST_DONE 0x8000 20 #define SISF_BIST_ERROR 0x4000 21 #define SISF_GATED_CLK 0x2000 22 #define SISF_DMA64 0x1000 [all …]
|
/openbmc/u-boot/arch/xtensa/dts/ |
H A D | ml605.dts | 8 …bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root… 11 memory@0 { 13 reg = <0x00000000 0x18000000>;
|
/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm4708-buffalo-wzr-1166dhp.dts | 20 memory@0 { 22 reg = <0x00000000 0x08000000>, 23 <0x88000000 0x18000000>;
|