/openbmc/linux/drivers/phy/renesas/ |
H A D | r8a779f0-ether-serdes.c | 18 #define R8A779F0_ETH_SERDES_OFFSET 0x0400 19 #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc 78 for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { in r8a779f0_eth_serdes_common_init_ram() 80 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram() 85 r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03); in r8a779f0_eth_serdes_common_init_ram() 97 r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097); in r8a779f0_eth_serdes_common_setting() 98 r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060); in r8a779f0_eth_serdes_common_setting() 99 r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200); in r8a779f0_eth_serdes_common_setting() 100 r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000); in r8a779f0_eth_serdes_common_setting() 101 r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d); in r8a779f0_eth_serdes_common_setting() [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx53-ppd.dts | 63 reg = <0x70000000 0x20000000>, 64 <0xb0000000 0x20000000>; 69 #clock-cells = <0>; 75 #clock-cells = <0>; 106 pinctrl-0 = <&pinctrl_usb_otg_vbus>; 125 pinctrl-0 = <&pinctrl_usbh2_vbus>; 136 pinctrl-0 = <&pinctrl_usbh3_vbus>; 170 pwms = <&pwm2 0 50000>; 171 brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 180 default-brightness-level = <0>; [all …]
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H A D | imx53-cx9020.dts | 20 reg = <0x70000000 0x20000000>, 21 <0xb0000000 0x20000000>; 24 display-0 { 26 #size-cells = <0>; 30 pinctrl-0 = <&pinctrl_ipu_disp0>; 32 port@0 { 33 reg = <0>; 66 #size-cells = <0>; 68 port@0 { 69 reg = <0>; [all …]
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H A D | imx53-qsb-common.dtsi | 15 reg = <0x70000000 0x20000000>, 16 <0xb0000000 0x20000000>; 21 pwms = <&pwm2 0 5000000 0>; 22 brightness-levels = <0 4 8 16 32 64 128 255>; 29 pinctrl-0 = <&pinctrl_ipu_disp0>; 32 #size-cells = <0>; 35 port@0 { 36 reg = <0>; 79 pinctrl-0 = <&led_pin_gpio7_7>; 83 gpios = <&gpio7 7 0>; [all …]
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/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_dump.h | 22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80 23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80 24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80 25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80 45 #define BNX2X_DUMP_VERSION 0x61111111 65 static const u32 page_vals_e2[] = {0, 128}; 68 {0x58000, 4608, DUMP_CHIP_E2, 0x30} 74 static const u32 page_vals_e3[] = {0, 128}; 77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30} 81 { 0x2000, 1, 0x1f, 0xfff}, [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx53-cx9020.dts | 11 #define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 12 #define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 13 #define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 14 #define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 27 pinctrl-0 = <&pinctrl_hog>; 32 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 33 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 34 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 35 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 36 MX53_PAD_GPIO_1__GPIO1_1 0x80000000 [all …]
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H A D | imx53-kp.dts | 24 pinctrl-0 = <&pinctrl_eth>; 32 pinctrl-0 = <&pinctrl_i2c2>; 43 reg = <0x8>; 49 pinctrl-0 = <&pinctrl_i2c3>; 61 pinctrl-0 = <&pinctrl_hog>; 66 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 67 MX53_PAD_FEC_MDC__FEC_MDC 0x4 68 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 69 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 70 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt8195-scp_adsp.c | 14 .set_ofs = 0x180, 15 .clr_ofs = 0x180, 16 .sta_ofs = 0x180, 23 GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "top_adsp", 0),
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H A D | clk-mt8192-scp_adsp.c | 16 .set_ofs = 0x180, 17 .clr_ofs = 0x180, 18 .sta_ofs = 0x180, 25 GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0),
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/openbmc/linux/drivers/gpu/drm/mxsfb/ |
H A D | lcdif_kms.c | 72 CSC0_COEF0_A1(0x12a) | CSC0_COEF0_A2(0x000), 73 CSC0_COEF1_A3(0x199) | CSC0_COEF1_B1(0x12a), 74 CSC0_COEF2_B2(0x79c) | CSC0_COEF2_B3(0x730), 75 CSC0_COEF3_C1(0x12a) | CSC0_COEF3_C2(0x204), 76 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x1f0), 77 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 83 * |R| |1.0000 0.0000 1.4020| |Y - 0 | 87 CSC0_COEF0_A1(0x100) | CSC0_COEF0_A2(0x000), 88 CSC0_COEF1_A3(0x167) | CSC0_COEF1_B1(0x100), 89 CSC0_COEF2_B2(0x7a8) | CSC0_COEF2_B3(0x749), [all …]
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/openbmc/linux/drivers/media/platform/chips-media/ |
H A D | coda_regs.h | 14 #define CODA_REG_BIT_CODE_RUN 0x000 15 #define CODA_REG_RUN_ENABLE (1 << 0) 16 #define CODA_REG_BIT_CODE_DOWN 0x004 17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16) 18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff) 19 #define CODA_REG_BIT_HOST_IN_REQ 0x008 20 #define CODA_REG_BIT_INT_CLEAR 0x00c 21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1 22 #define CODA_REG_BIT_INT_STATUS 0x010 23 #define CODA_REG_BIT_CODE_RESET 0x014 [all …]
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/openbmc/u-boot/drivers/clk/renesas/ |
H A D | r8a7795-cpg-mssr.c | 96 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), 97 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), 98 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), 99 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), 101 DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), 114 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), 275 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 276 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 277 * 0 0 1 0 Prohibited setting 278 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 [all …]
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H A D | r8a7796-cpg-mssr.c | 96 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), 97 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), 98 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), 99 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), 101 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238), 248 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 249 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 250 * 0 0 1 0 Prohibited setting 251 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 252 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 [all …]
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/openbmc/u-boot/board/intel/cougarcanyon2/ |
H A D | cougarcanyon2.c | 16 #define SIO1007_RUNTIME_IOPORT 0x180 33 (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN); in board_early_init_f() 37 /* Enable legacy serial port at 0x3f8 */ in board_early_init_f() 38 sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ); in board_early_init_f() 40 /* Enable SIO1007 runtime I/O port at 0x180 */ in board_early_init_f() 45 * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007. in board_early_init_f() 48 sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT, in board_early_init_f() 50 sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1); in board_early_init_f() 52 return 0; in board_early_init_f()
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/openbmc/linux/sound/pci/oxygen/ |
H A D | wm8766.h | 5 #define WM8766_LDA1 0x00 6 #define WM8766_RDA1 0x01 7 #define WM8766_DAC_CTRL 0x02 8 #define WM8766_INT_CTRL 0x03 9 #define WM8766_LDA2 0x04 10 #define WM8766_RDA2 0x05 11 #define WM8766_LDA3 0x06 12 #define WM8766_RDA3 0x07 13 #define WM8766_MASTDA 0x08 14 #define WM8766_DAC_CTRL2 0x09 [all …]
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H A D | wm8776.h | 14 #define WM8776_HPLVOL 0x00 15 #define WM8776_HPRVOL 0x01 16 #define WM8776_HPMASTER 0x02 17 #define WM8776_DACLVOL 0x03 18 #define WM8776_DACRVOL 0x04 19 #define WM8776_DACMASTER 0x05 20 #define WM8776_PHASESWAP 0x06 21 #define WM8776_DACCTRL1 0x07 22 #define WM8776_DACMUTE 0x08 23 #define WM8776_DACCTRL2 0x09 [all …]
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/openbmc/linux/drivers/clk/renesas/ |
H A D | r8a774b1-cpg-mssr.c | 97 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), 98 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), 99 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), 100 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), 101 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), 102 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), 103 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), 104 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), 113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), [all …]
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H A D | r8a774a1-cpg-mssr.c | 78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 100 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), 116 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a774e1-cpg-mssr.c | 78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 100 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c), 117 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a77965-cpg-mssr.c | 101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074), 102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078), 103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268), 104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c), 105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074), 106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078), 107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268), 108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c), 118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), [all …]
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H A D | r8a7796-cpg-mssr.c | 83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 106 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074), 107 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078), 108 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268), 109 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c), 110 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074), 111 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078), 112 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), 113 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), 123 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a7795-cpg-mssr.c | 81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 104 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074), 105 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078), 106 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268), 107 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c), 108 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074), 109 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078), 110 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), 111 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), 121 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | faraday,ftgmac100.yaml | 80 reg = <0x1e660000 0x180>; 87 reg = <0x1e680000 0x180>; 95 #size-cells = <0>;
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/openbmc/linux/arch/m68k/include/asm/ |
H A D | m525xsim.h | 30 #define MCF_MBAR2 0x80000000 35 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 37 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 38 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ 39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 40 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ [all …]
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/openbmc/linux/sound/soc/codecs/ |
H A D | wm8770.c | 37 { 0, 0x7f }, 38 { 1, 0x7f }, 39 { 2, 0x7f }, 40 { 3, 0x7f }, 41 { 4, 0x7f }, 42 { 5, 0x7f }, 43 { 6, 0x7f }, 44 { 7, 0x7f }, 45 { 8, 0x7f }, 46 { 9, 0xff }, [all …]
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