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/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
62 reg = <0x0 0x100>;
80 reg = <0x0 0x200>;
98 reg = <0x0 0x300>;
116 reg = <0x0 0x400>;
134 reg = <0x0 0x500>;
[all …]
H A Dsdx75.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dqdu1000.dtsi24 #size-cells = <0>;
26 CPU0: cpu@0 {
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
34 qcom,freq-domains = <&cpufreq_hw 0>;
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domains = <&cpufreq_hw 0>;
70 reg = <0x0 0x200>;
71 clocks = <&cpufreq_hw 0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]