Searched +full:0 +full:x12e00000 (Results 1 – 6 of 6) sorted by relevance
101 reg = <0x12e00000 0x1000>;104 #size-cells = <0>;111 reg = <0x66>;121 reg = <0x138c0000 0xc0>;124 #size-cells = <0>;131 reg = <0x66>;
46 reg = <0x12D10000 0x100>;47 interrupts = <0 106 0>;53 #size-cells = <0>;55 reg = <0x12CA0000 0x100>;56 interrupts = <0 60 0>;61 #size-cells = <0>;63 reg = <0x12CB0000 0x100>;64 interrupts = <0 61 0>;69 #size-cells = <0>;71 reg = <0x12CC0000 0x100>;[all …]
10 #define DEVICE_NOT_AVAILABLE 013 #define EXYNOS4_ADDR_BASE 0x1000000016 #define EXYNOS4_I2C_SPACING 0x1000018 #define EXYNOS4_GPIO_PART3_BASE 0x0386000019 #define EXYNOS4_PRO_ID 0x1000000020 #define EXYNOS4_SYSREG_BASE 0x1001000021 #define EXYNOS4_POWER_BASE 0x1002000022 #define EXYNOS4_SWRESET 0x1002040023 #define EXYNOS4_CLOCK_BASE 0x1003000024 #define EXYNOS4_SYSTIMER_BASE 0x10050000[all …]
16 #size-cells = <0>;20 cpu@0 {23 reg = <0>;62 reg = <0x0c000000 0x600000>;63 ranges = <0x0 0x0c000000 0x600000>;68 reg = <0x5f0000 0x8000>;78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */[all …]
16 #size-cells = <0>;20 cpu@0 {23 reg = <0>;49 reg = <0x02348400 0x100>;59 reg = <0x02348800 0x100>;66 reg = <0x02348000 0x100>;110 reg = <0x02620690 0xc>;112 #size-cells = <0>;116 pinctrl-single,function-mask = <0x1>;122 0x0 0x0 0xc0[all …]
153 cluster_a15_opp_table: opp-table-0 {270 reg = <0x10d20000 0x1000>;271 ranges = <0x0 0x10d20000 0x6000>;276 reg = <0x4000 0x1000>;281 reg = <0x5000 0x1000>;287 reg = <0x10010000 0x30000>;293 reg = <0x03810000 0x0c>;303 reg = <0x11000000 0x10000>;316 #size-cells = <0>;317 reg = <0x12200000 0x2000>;[all …]