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/openbmc/linux/Documentation/devicetree/bindings/gpu/
H A Dsamsung-g2d.yaml69 reg = <0x12800000 0x1000>;
70 interrupts = <0 89 0>;
H A Dsamsung-scaler.yaml75 reg = <0x12800000 0x1294>;
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4210.dtsi37 reg = <0x10023CA0 0x20>;
41 cpu-offset = <0x8000>;
46 reg = <0x10050000 0x800>;
48 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 interrupt-map = <0 &gic 0 57 0>,
57 <1 &gic 0 69 0>,
60 <4 &gic 0 42 0>,
61 <5 &gic 0 48 0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
H A Dkeystone-k2l.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
49 reg = <0x02348400 0x100>;
59 reg = <0x02348800 0x100>;
66 reg = <0x02348000 0x100>;
110 reg = <0x02620690 0xc>;
112 #size-cells = <0>;
116 pinctrl-single,function-mask = <0x1>;
122 0x0 0x0 0xc0
[all …]
/openbmc/u-boot/include/configs/
H A Ddisplay5.h14 #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
18 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00
21 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x100 /* 128KiB */
29 * 0x000000 - 0x020000 : SPI.SPL (128KiB)
30 * 0x020000 - 0x120000 : SPI.u-boot (1MiB)
31 * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB)
32 * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB)
33 * 0x140000 - 0x540000 : SPI.swupdate-kernel-FIT (4MiB)
34 * 0x540000 - 0x1540000 : SPI.swupdate-initramfs (16MiB)
35 * 0x1540000 - 0x1640000 : SPI.factory (1MiB)
[all …]
/openbmc/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/openbmc/qemu/hw/sparc/
H A Dleon3.c54 #define LEON3_PROM_OFFSET (0x00000000)
55 #define LEON3_RAM_OFFSET (0x40000000)
59 #define LEON3_UART_OFFSET (0x80000100)
62 #define LEON3_IRQMP_OFFSET (0x80000200)
64 #define LEON3_TIMER_OFFSET (0x80000300)
68 #define LEON3_APB_PNP_OFFSET (0x800FF000)
69 #define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
81 stl_p(code++, 0x82100000); /* mov %g0, %g1 */ in gen_store_u32()
82 stl_p(code++, 0x84100000); /* mov %g0, %g2 */ in gen_store_u32()
83 stl_p(code++, 0x03000000 + in gen_store_u32()
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi34 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #clock-cells = <0>;
57 #size-cells = <0>;
59 cpu0: cpu@0 {
62 reg = <0x000>;
73 performance-domains = <&performance 0>;
80 reg = <0x100>;
91 performance-domains = <&performance 0>;
98 reg = <0x200>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgk104.c144 u32 addr = 0x110974, i; in gk104_ram_train()
146 ram_mask(fuc, 0x10f910, mask, data); in gk104_ram_train()
147 ram_mask(fuc, 0x10f914, mask, data); in gk104_ram_train()
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { in gk104_ram_train()
152 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); in gk104_ram_train()
166 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); in r1373f4_init()
167 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); in r1373f4_init()
169 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); in r1373f4_init()
172 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); in r1373f4_init()
173 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); in r1373f4_init()
[all …]
H A Dramgt215.c103 u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; in gt215_link_train_calc()
105 for (i = 0; i < 8; i++) { in gt215_link_train_calc()
106 for (lo = 0; lo < 0x40; lo++) { in gt215_link_train_calc()
107 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
109 if (vals[lo] & (0x101 << i)) in gt215_link_train_calc()
113 if (lo == 0x40) in gt215_link_train_calc()
116 for (hi = lo + 1; hi < 0x40; hi++) { in gt215_link_train_calc()
117 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
119 if (!(vals[hi] & (0x101 << i))) { in gt215_link_train_calc()
126 bins[(median[i] & 0xf0) >> 4]++; in gt215_link_train_calc()
[all …]
/openbmc/linux/Documentation/admin-guide/media/
H A Dvivid.rst63 hexadecimal values, one for each instance. The default is 0x1d3d.
66 - bit 0: Video Capture node
67 - bit 2-3: VBI Capture node: 0 = none, 1 = raw vbi, 2 = sliced vbi, 3 = both
71 - bit 10-11: VBI Output node: 0 = none, 1 = raw vbi, 2 = sliced vbi, 3 = both
84 n_devs=4 node_types=0x1,0x1,0x100,0x100
94 the input types for each instance, the default is 0xe4. This defines
97 pair gives the type and bits 0-1 map to input 0, bits 2-3 map to input 1,
105 So to create a video capture device with 8 inputs where input 0 is a TV
111 num_inputs=8 input_types=0xffa9
121 the output types for each instance, the default is 0x02. This defines
[all …]
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc20 QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
71 tcg_debug_assert(slot >= 0 && slot <= 1);
87 if (offset == sextract64(offset, 0, 26)) {
90 *src_rw = deposit32(*src_rw, 0, 26, offset);
101 if (offset == sextract64(offset, 0, 19)) {
113 if (offset == sextract64(offset, 0, 14)) {
123 tcg_debug_assert(addend == 0);
137 #define TCG_CT_CONST_AIMM 0x100
138 #define TCG_CT_CONST_LIMM 0x200
139 #define TCG_CT_CONST_ZERO 0x400
[all …]