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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]