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/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,gsbi.yaml20 A GSBI controller node can contain 0 or more child nodes representing serial
68 "spi@[0-9a-f]+$":
72 "i2c@[0-9a-f]+$":
76 "serial@[0-9a-f]+$":
98 reg = <0x12440000 0x100>;
111 reg = <0x12450000 0x100>,
112 <0x12400000 0x03>;
113 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
120 reg = <0x12460000 0x1000>;
121 pinctrl-0 = <&i2c1_pins>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
110 #clock-cells = <0>;
112 clock-frequency = <0>;
117 #clock-cells = <0>;
119 clock-frequency = <0>;
124 #clock-cells = <0>;
126 clock-frequency = <0>;
131 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
[all …]
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]