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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsamsung,exynos-dw-mshc.yaml46 minimum: 0
55 minimum: 0
58 minimum: 0
69 minimum: 0
72 minimum: 0
78 - valid value for tx phase shift and rx phase shift is 0 to 7.
81 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
82 phase shift clocks should be 0.
89 minimum: 0
92 minimum: 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5.dtsi20 reg = <0x10440000 0x1000>;
21 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
22 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
23 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
24 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
25 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
26 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
27 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
28 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
35 reg = <0x10481000 0x1000>,
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0c>;
92 reg = <0x10060000 0x100>;
[all …]
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]