Searched +full:0 +full:x11700000 (Results 1 – 4 of 4) sorted by relevance
35 reg = <0x10800000 0x1>, <0x11700000 0x1>;
32 where N starting from 0 to one less than the number of root ports.80 reg = <0 0x1a000000 0 0x1000>;88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */89 <0 0x1a142000 0 0x1000>, /* Port0 registers */90 <0 0x1a143000 0 0x1000>, /* Port1 registers */91 <0 0x1a144000 0 0x1000>; /* Port2 registers */96 interrupt-map-mask = <0xf800 0 0 0>;97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;[all …]
22 cluster0_opp: opp-table-0 {66 #size-cells = <0>;85 cpu0: cpu@0 {88 reg = <0x000>;100 reg = <0x001>;113 reg = <0x200>;126 CPU_SLEEP_0: cpu-sleep-0 {132 arm,psci-suspend-param = <0x0010000>;135 CLUSTER_SLEEP_0: cluster-sleep-0 {141 arm,psci-suspend-param = <0x1010000>;[all …]
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */[all …]