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Searched +full:0 +full:x108000 (Results 1 – 22 of 22) sorted by relevance

/openbmc/qemu/tests/qemu-iotests/tests/
H A Dimage-fleecing.out23 read -P0x5d 0 64k
26 read -P0xcd 0x3ff0000 64k
27 read -P0 0x00f8000 32k
28 read -P0 0x2010000 32k
29 read -P0 0x3fe0000 64k
33 write -P0xab 0 64k
35 write -P0xad 0x00f8000 64k
37 write -P0x1d 0x2008000 64k
39 write -P0xea 0x3fe0000 64k
44 read -P0x5d 0 64k
[all …]
H A Dimage-fleecing37 patterns = [('0x5d', '0', '64k'),
38 ('0xd5', '1M', '64k'),
39 ('0xdc', '32M', '64k'),
40 ('0xcd', '0x3ff0000', '64k')] # 64M - 64K
42 overwrite = [('0xab', '0', '64k'), # Full overwrite
43 ('0xad', '0x00f8000', '64k'), # Partial-left (1M-32K)
44 ('0x1d', '0x2008000', '64k'), # Partial-right (32M+32K)
45 ('0xea', '0x3fe0000', '64k')] # Adjacent-left (64M - 128K)
47 zeroes = [('0', '0x00f8000', '32k'), # Left-end of partial-left (1M-32K)
48 ('0', '0x2010000', '32k'), # Right-end of partial-right (32M+64K)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpm.yaml72 reg = <0x108000 0x1000>;
73 qcom,ipc = <&apcs 0x8 2>;
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
H A Db4420si-post.dtsi37 /* controller at 0x200000 */
43 dcsr-epu@0 {
70 reg = <0x108000 0x1000 0x109000 0x1000>;
94 reg = <0xc20000 0x40000>;
H A Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
[all …]
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/openbmc/linux/sound/pci/mixart/
H A Dmixart_hwdep.h31 #define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x))
36 #define DAUGHTER_TYPE_MASK 0x0F
37 #define DAUGHTER_VER_MASK 0xF0
40 #define MIXART_DAUGHTER_TYPE_NONE 0x00
41 #define MIXART_DAUGHTER_TYPE_COBRANET 0x08
42 #define MIXART_DAUGHTER_TYPE_AES 0x0E
50 …* -----------BAR 0 -------------------------------------------------------------------------------…
52 #define MIXART_PSEUDOREG 0x2000 /* base address for ps…
54 #define MIXART_PSEUDOREG_BOARDNUMBER MIXART_PSEUDOREG+0 /* board number */
57 #define MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET MIXART_PSEUDOREG+0x70 /* streaming load */
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304>;
23 cpu@0 {
27 reg = <0>;
52 reg = <0x0 0x0>;
57 interrupts = <GIC_PPI 10 0x304>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
103 reg = <0x02000000 0x1000>,
[all …]
H A Dqcom-mdm9615.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0>;
45 #clock-cells = <0>;
66 reg = <0x02040000 0x1000>;
67 arm,data-latency = <2 2 0>;
76 reg = <0x02000000 0x1000>,
77 <0x02002000 0x1000>;
86 reg = <0x0200a000 0x100>;
88 cpu-offset = <0x80000>;
[all …]
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/openbmc/linux/sound/pci/ctxfi/
H A Dct20k1reg.h10 #define DSPXRAM_START 0x000000
11 #define DSPXRAM_END 0x013FFC
12 #define DSPAXRAM_START 0x020000
13 #define DSPAXRAM_END 0x023FFC
14 #define DSPYRAM_START 0x040000
15 #define DSPYRAM_END 0x04FFFC
16 #define DSPAYRAM_START 0x020000
17 #define DSPAYRAM_END 0x063FFC
18 #define DSPMICRO_START 0x080000
19 #define DSPMICRO_END 0x0B3FFC
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_cmd.h14 #define HCLGE_CMDQ_RX_INVLD_B 0
26 #define HCLGE_TQP_REG_OFFSET 0x80000
27 #define HCLGE_TQP_REG_SIZE 0x200
30 #define HCLGE_TQP_EXT_REG_OFFSET 0x100
33 #define HCLGE_RCB_INIT_FLAG_EN_B 0
43 #define HCLGE_TQP_MAP_TYPE_PF 0
45 #define HCLGE_TQP_MAP_TYPE_B 0
61 #define HCLGE_VECTOR_ID_L_S 0
62 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)
65 #define HCLGE_INT_TYPE_S 0
[all …]
/openbmc/linux/include/soc/fsl/qe/
H A Dimmap_qe.h26 u8 res0[0x04];
28 u8 res1[0x70];
44 u8 res0[0x4];
47 u8 res1[0x4];
49 u8 res2[0x20];
51 u8 res3[0x1C];
59 u8 res0[0xA];
61 u8 res1[0x2];
66 u8 res2[0x8];
70 u8 res3[0x2];
[all …]
/openbmc/u-boot/include/linux/
H A Dimmap_qe.h16 #define QE_MURAM_SIZE 0xc000UL
20 #define QE_MURAM_SIZE 0x4000UL
27 #define QE_MURAM_SIZE 0x6000UL
33 #define QE_IMMR_OFFSET 0x00140000
35 #define QE_IMMR_OFFSET 0x01400000
42 u8 res0[0x4];
44 u8 res1[0x70];
60 u8 res0[0x4];
63 u8 res1[0x4];
65 u8 res2[0x20];
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]