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Searched +full:0 +full:x10680000 (Results 1 – 25 of 27) sorted by relevance

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/openbmc/linux/arch/sparc/lib/
H A DU3patch.S7 #define BRANCH_ALWAYS 0x10680000
8 #define NOP 0x01000000
23 stw %g3, [%g2 + 0x4]; \
H A DNG2patch.S7 #define BRANCH_ALWAYS 0x10680000
8 #define NOP 0x01000000
23 stw %g3, [%g2 + 0x4]; \
H A DGENpatch.S7 #define BRANCH_ALWAYS 0x10680000
8 #define NOP 0x01000000
23 stw %g3, [%g2 + 0x4]; \
H A DNGpatch.S7 #define BRANCH_ALWAYS 0x10680000
8 #define NOP 0x01000000
23 stw %g3, [%g2 + 0x4]; \
H A DM7patch.S9 #define BRANCH_ALWAYS 0x10680000
10 #define NOP 0x01000000
25 stw %g3, [%g2 + 0x4]; \
H A DNG4patch.S9 #define BRANCH_ALWAYS 0x10680000
10 #define NOP 0x01000000
25 stw %g3, [%g2 + 0x4]; \
H A DGENpage.S13 1: ldx [%o1 + 0x00], %o2
14 ldx [%o1 + 0x08], %o3
15 ldx [%o1 + 0x10], %o4
16 ldx [%o1 + 0x18], %o5
17 stx %o2, [%o0 + 0x00]
18 stx %o3, [%o0 + 0x08]
19 stx %o4, [%o0 + 0x10]
20 stx %o5, [%o0 + 0x18]
21 ldx [%o1 + 0x20], %o2
22 ldx [%o1 + 0x28], %o3
[all …]
H A DNGbzero.S21 and %o1, 0xff, %o3
45 wr %o4, 0x0, %asi
50 andcc %o0, 0x7, %g1
55 1: EX_ST(stba %o2, [%o0 + 0x00] %asi)
66 1: EX_ST(stxa %o2, [%o0 + 0x00] %asi)
72 wr %g7, 0x0, %asi
76 EX_ST(stxa %o2, [%o0 + 0x00] %asi)
77 EX_ST(stxa %o2, [%o0 + 0x08] %asi)
78 EX_ST(stxa %o2, [%o0 + 0x10] %asi)
79 EX_ST(stxa %o2, [%o0 + 0x18] %asi)
[all …]
H A DGENbzero.S22 and %o1, 0xff, %o3
44 wr %o4, 0x0, %asi
49 andcc %o0, 0x7, %g1
54 1: EX_ST(stba %o2, [%o0 + 0x00] %asi)
65 1: EX_ST(stxa %o2, [%o0 + 0x00] %asi)
74 EX_ST(stxa %o2, [%o0 + 0x00] %asi)
75 EX_ST(stxa %o2, [%o0 + 0x08] %asi)
76 EX_ST(stxa %o2, [%o0 + 0x10] %asi)
77 EX_ST(stxa %o2, [%o0 + 0x18] %asi)
78 EX_ST(stxa %o2, [%o0 + 0x20] %asi)
[all …]
H A DNGpage.S24 prefetch [%i1 + 0x00], #one_read
25 prefetch [%i1 + 0x40], #one_read
27 1: prefetch [%i1 + 0x80], #one_read
28 prefetch [%i1 + 0xc0], #one_read
29 ldda [%i1 + 0x00] %asi, %o2
30 ldda [%i1 + 0x10] %asi, %o4
31 ldda [%i1 + 0x20] %asi, %l2
32 ldda [%i1 + 0x30] %asi, %l4
33 stxa %o2, [%i0 + 0x00] %asi
34 stxa %o3, [%i0 + 0x08] %asi
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Djump_label.c25 if (off <= 0xfffff && off >= -0x100000) in arch_jump_label_transform()
31 val = 0x10680000 | (((u32) off >> 2) & 0x7ffff); in arch_jump_label_transform()
34 BUG_ON(off > 0x7fffff); in arch_jump_label_transform()
35 BUG_ON(off < -0x800000); in arch_jump_label_transform()
37 val = 0x10800000 | (((u32) off >> 2) & 0x3fffff); in arch_jump_label_transform()
40 val = 0x01000000; in arch_jump_label_transform()
H A Dsun4v_tlb_miss.S31 * index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
32 * tsb_base = tsb_reg & ~0x7UL;
37 and TSB_PTR, 0x7, TMP1; \
39 andn TSB_PTR, 0x7, TSB_PTR; \
398 #define BRANCH_ALWAYS 0x10680000
399 #define NOP 0x01000000
414 stw %g3, [%g2 + 0x4]; \
/openbmc/linux/Documentation/devicetree/bindings/dsp/
H A Dmediatek,mt8186-dsp.yaml81 reg = <0x10680000 0x2000>,
82 <0x10800000 0x100000>,
83 <0x1068b000 0x100>,
84 <0x1068f000 0x1000>;
/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
18 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
35 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
44 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
45 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
[all …]
/openbmc/u-boot/board/ebv/socrates/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/devboards/dbm-soc1/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/samtec/vining_fpga/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/sr1500/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/terasic/sockit/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/is1/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/altera/cyclone5-socdk/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/openbmc/linux/arch/mips/alchemy/common/
H A Ddbdma.c68 { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
69 { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
70 { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
71 { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
74 { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
75 { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
76 { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
77 { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
80 { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
81 { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
[all …]

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