Searched +full:0 +full:x100c0000 (Results 1 – 9 of 9) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/thermal/ |
H A D | samsung,exynos-thermal.yaml | 24 # For TMU channel 0, 1 on Exynos5420: 59 TRIMINFO at 0x1006c000 contains data for TMU channel 3 60 TRIMINFO at 0x100a0000 contains data for TMU channel 4 61 TRIMINFO at 0x10068000 contains data for TMU channel 2 150 reg = <0x100C0000 0x100>; 153 #thermal-sensor-cells = <0>; 164 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 166 #thermal-sensor-cells = <0>; 177 reg = <0x10060000 0x200>; 179 #thermal-sensor-cells = <0>;
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/openbmc/u-boot/arch/arm/dts/ |
H A D | exynos4210.dtsi | 37 reg = <0x10023CA0 0x20>; 41 cpu-offset = <0x8000>; 46 reg = <0x10050000 0x800>; 48 interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 54 #address-cells = <0>; 55 #size-cells = <0>; 56 interrupt-map = <0 &gic 0 57 0>, 57 <1 &gic 0 69 0>, 60 <4 &gic 0 42 0>, 61 <5 &gic 0 48 0>; [all …]
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H A D | rk322x.dtsi | 29 #size-cells = <0>; 34 reg = <0xf00>; 48 reg = <0xf01>; 55 reg = <0xf02>; 62 reg = <0xf03>; 75 reg = <0x110f0000 0x4000>; 76 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 107 #clock-cells = <0>; 112 reg = <0x10080000 0x9000>; 115 ranges = <0 0x10080000 0x9000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos4x12.dtsi | 70 #interconnect-cells = <0>; 80 #interconnect-cells = <0>; 120 #interconnect-cells = <0>; 211 reg = <0x11400000 0x1000>; 217 reg = <0x11000000 0x1000>; 229 reg = <0x03860000 0x1000>; 231 interrupts = <10 0>; 236 reg = <0x106e0000 0x1000>; 242 reg = <0x02020000 0x40000>; 245 ranges = <0 0x02020000 0x40000>; [all …]
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H A D | exynos3250.dtsi | 199 #size-cells = <0>; 212 cpu0: cpu@0 { 215 reg = <0>; 259 xusbxti: clock-0 { 261 clock-frequency = <0>; 262 #clock-cells = <0>; 268 clock-frequency = <0>; 269 #clock-cells = <0>; 275 clock-frequency = <0>; 276 #clock-cells = <0>; [all …]
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H A D | exynos4.dtsi | 68 reg = <0x03810000 0x0c>; 79 reg = <0x03830000 0x100>; 88 samsung,idma-addr = <0x03000000>; 95 reg = <0x10000000 0x100>; 100 reg = <0x10500000 0x2000>; 105 reg = <0x12570000 0x14>; 110 reg = <0x10023c40 0x20>; 111 #power-domain-cells = <0>; 117 reg = <0x10023c60 0x20>; 118 #power-domain-cells = <0>; [all …]
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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_main.c | 55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd.dtsi | 39 #size-cells = <0>; 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 92 reg = <0x0 0x000>; 96 i-cache-size = <0xc000>; 99 d-cache-size = <0x8000>; 108 reg = <0x0 0x001>; 112 i-cache-size = <0xc000>; 115 d-cache-size = <0x8000>; 124 reg = <0x0 0x002>; [all …]
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/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk322x.dtsi | 26 #size-cells = <0>; 31 reg = <0xf00>; 43 reg = <0xf01>; 53 reg = <0xf02>; 63 reg = <0xf03>; 71 cpu0_opp_table: opp-table-0 { 127 #clock-cells = <0>; 137 reg = <0x100b0000 0x4000>; 144 pinctrl-0 = <&i2s1_bus>; 150 reg = <0x100c0000 0x4000>; [all …]
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