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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-femac.txt32 reg = <0x10090000 0x1000>,<0x10091300 0x200>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dstarfive,jh7110-tdm.yaml64 const: 0
82 reg = <0x10090000 0x1000>;
97 #sound-dai-cells = <0>;
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
168 reg = <0x0 0xc000000 0x0 0x4000000>;
169 #address-cells = <0>;
173 <&cpu0_intc 0xffffffff>,
174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi35 #clock-cells = <0>;
41 reg = <0x10090000 0x10000>;
52 reg = <0x10104000 0x800>;
64 reg = <0x10138000 0x1000>;
71 reg = <0x1013c000 0x100>;
76 reg = <0x1013c200 0x20>;
90 reg = <0x1013c600 0x20>;
99 reg = <0x1013d000 0x1000>,
100 <0x1013c100 0x0100>;
105 reg = <0x10124000 0x400>;
[all …]
H A Drk3036.dtsi34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.sifive-fu54069 Hit any key to stop autoboot: 0
73 riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
88 boot_params = 0x0000000000000000
89 DRAM bank = 0x0000000000000000
90 -> start = 0x0000000080000000
91 -> size = 0x0000000200000000
92 relocaddr = 0x00000000fff90000
93 reloc off = 0x000000007fd90000
98 ethernet@10090000: PHY present at 0
101 ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3800)
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
185 cpu_opp: opp-table-0 {
245 #clock-cells = <0>;
250 #clock-cells = <0>;
256 #clock-cells = <0>;
262 #clock-cells = <0>;
268 #clock-cells = <0>;
274 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c10 * 0) UART
69 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
70 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
72 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
73 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
74 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
75 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
76 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
77 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
[all …]