Home
last modified time | relevance | path

Searched +full:0 +full:x1000b000 (Results 1 – 25 of 35) sorted by relevance

12

/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Dimx-uart.h9 #define IMX1_UART1_BASE_ADDR 0x00206000
10 #define IMX1_UART2_BASE_ADDR 0x00207000
14 #define IMX25_UART1_BASE_ADDR 0x43f90000
15 #define IMX25_UART2_BASE_ADDR 0x43f94000
16 #define IMX25_UART3_BASE_ADDR 0x5000c000
17 #define IMX25_UART4_BASE_ADDR 0x50008000
18 #define IMX25_UART5_BASE_ADDR 0x5002c000
22 #define IMX27_UART1_BASE_ADDR 0x1000a000
23 #define IMX27_UART2_BASE_ADDR 0x1000b000
24 #define IMX27_UART3_BASE_ADDR 0x1000c000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8192-pinctrl.yaml149 reg = <0x10005000 0x1000>,
150 <0x11c20000 0x1000>,
151 <0x11d10000 0x1000>,
152 <0x11d30000 0x1000>,
153 <0x11d40000 0x1000>,
154 <0x11e20000 0x1000>,
155 <0x11e70000 0x1000>,
156 <0x11ea0000 0x1000>,
157 <0x11f20000 0x1000>,
158 <0x11f30000 0x1000>,
[all …]
H A Dmediatek,mt65xx-pinctrl.yaml141 reg = <0 0x10005000 0 0x1000>;
146 reg = <0 0x1020C020 0 0x1000>;
151 reg = <0 0x1000B000 0 0x1000>;
H A Dmediatek,mt6779-pinctrl.yaml114 '-[0-9]*$':
158 enum: [0, 1]
165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
170 enum: [0, 1, 2, 3]
177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
182 enum: [0, 1, 2, 3]
[all …]
H A Dmediatek,mt6795-pinctrl.yaml136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
141 enum: [0, 1, 2, 3]
148 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
149 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
150 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
153 enum: [0, 1, 2, 3]
186 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
190 gpio-ranges = <&pio 0 0 196>;
H A Dmediatek,mt8188-pinctrl.yaml188 reg = <0x10005000 0x1000>,
189 <0x11c00000 0x1000>,
190 <0x11e10000 0x1000>,
191 <0x11e20000 0x1000>,
192 <0x11ea0000 0x1000>,
193 <0x1000b000 0x1000>;
199 gpio-ranges = <&pio 0 0 176>;
201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8186-pinctrl.yaml229 reg = <0x10005000 0x1000>,
230 <0x10002000 0x0200>,
231 <0x10002200 0x0200>,
232 <0x10002400 0x0200>,
233 <0x10002600 0x0200>,
234 <0x10002A00 0x0200>,
235 <0x10002c00 0x0200>,
236 <0x1000b000 0x1000>;
242 gpio-ranges = <&pio 0 0 185>;
244 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8195-pinctrl.yaml240 reg = <0x10005000 0x1000>,
241 <0x11d10000 0x1000>,
242 <0x11d30000 0x1000>,
243 <0x11d40000 0x1000>,
244 <0x11e20000 0x1000>,
245 <0x11eb0000 0x1000>,
246 <0x11f40000 0x1000>,
247 <0x1000b000 0x1000>;
253 gpio-ranges = <&pio 0 0 144>;
255 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8183-pinctrl.yaml126 When E1=0/E0=0, the strength is 0.125mA.
127 When E1=0/E0=1, the strength is 0.25mA.
128 When E1=1/E0=0, the strength is 0.5mA.
132 0: (E1, E0, EN) = (0, 0, 0)
133 1: (E1, E0, EN) = (0, 0, 1)
134 2: (E1, E0, EN) = (0, 1, 0)
135 3: (E1, E0, EN) = (0, 1, 1)
136 4: (E1, E0, EN) = (1, 0, 0)
137 5: (E1, E0, EN) = (1, 0, 1)
138 6: (E1, E0, EN) = (1, 1, 0)
[all …]
H A Dmediatek,mt8365-pinctrl.yaml83 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
84 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
85 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
97 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
98 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
99 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
130 When E1=0/E0=0, the strength is 0.125mA.
131 When E1=0/E0=1, the strength is 0.25mA.
132 When E1=1/E0=0, the strength is 0.5mA.
136 0: (E1, E0, EN) = (0, 0, 0)
[all …]
H A Dmediatek,mt7981-pinctrl.yaml85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
396 enum: [0, 1, 2, 3]
400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
[all …]
H A Dmediatek,mt7986-pinctrl.yaml86 "watchdog" "watchdog" 0
334 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
339 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
342 enum: [0, 1, 2, 3]
346 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
351 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
45 #size-cells = <0>;
53 #power-domain-cells = <0>;
62 #power-domain-cells = <0>;
69 #power-domain-cells = <0>;
78 #size-cells = <0>;
85 #size-cells = <0>;
[all …]
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
H A Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
H A Dmt8365.dtsi21 #size-cells = <0>;
23 cluster0_opp: opp-table-0 {
125 cpu0: cpu@0 {
128 reg = <0x0>;
132 i-cache-size = <0x8000>;
135 d-cache-size = <0x8000>;
148 reg = <0x1>;
152 i-cache-size = <0x8000>;
155 d-cache-size = <0x8000>;
168 reg = <0x2>;
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dversatile.c25 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
33 #define VERSATILE_SYS_PCICTL_OFFSET 0x44
34 #define VERSATILE_SYS_MCI_OFFSET 0x48
39 #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
40 #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
41 #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
46 #define VERSATILE_REFCLK 0
87 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
166 versatile_sys_base = of_iomap(np, 0); in versatile_dt_init()
/openbmc/qemu/hw/arm/
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
H A Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
118 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]

12