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/openbmc/linux/drivers/devfreq/event/
H A Drockchip-dfi.c26 #define DDRMON_CTRL 0x04
27 #define CLR_DDRMON_CTRL (0x1f0000 << 0)
28 #define LPDDR4_EN (0x10001 << 4)
29 #define HARDWARE_EN (0x10001 << 3)
30 #define LPDDR3_EN (0x10001 << 2)
31 #define SOFTWARE_EN (0x10001 << 1)
32 #define SOFTWARE_DIS (0x10000 << 1)
33 #define TIME_CNT_EN (0x10001 << 0)
35 #define DDRMON_CH0_COUNT_NUM 0x28
36 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
[all …]
/openbmc/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c19 #define PLL_IDIV_REG 0x0
20 #define PLL_FBDIV_REG 0x4
21 #define PLL_ODIV0_REG 0x8
22 #define PLL_ODIV1_REG 0xC
34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
36 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
37 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
38 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A Dother.json4 "EventCode": "0xc1",
7 "UMask": "0x4",
12 "EventCode": "0xc1",
15 "UMask": "0x8",
20 "EventCode": "0x28",
23 "UMask": "0x2",
28 "EventCode": "0x28",
31 "UMask": "0x4",
36 "EventCode": "0x28",
39 "UMask": "0x8",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Dother.json4 "EventCode": "0xB7",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10001",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x10002",
18 "UMask": "0x1"
/openbmc/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dother.json4 "EventCode": "0xB7",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10001",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x10002",
18 "UMask": "0x1"
/openbmc/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dother.json4 "EventCode": "0x2A,0x2B",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10001",
9 "UMask": "0x1"
13 "EventCode": "0x2A,0x2B",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x104000001",
18 "UMask": "0x1"
22 "EventCode": "0x2A,0x2B",
24 "MSRIndex": "0x1a6,0x1a7",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A Dother.json4 "EventCode": "0xB7",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10008",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x10001",
18 "UMask": "0x1"
22 "EventCode": "0xB7",
24 "MSRIndex": "0x1a6,0x1a7",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/openbmc/linux/drivers/thermal/
H A Drockchip_thermal.c28 TSHUT_MODE_CRU = 0,
35 * 0: low active, 1: high active
38 TSHUT_LOW_ACTIVE = 0,
48 ADC_DECREMENT = 0,
73 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
74 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
136 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
137 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
164 #define TSADCV2_USER_CON 0x00
165 #define TSADCV2_AUTO_CON 0x04
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0043-firmware-psci-Fix-bind_smccc_features-psci-check.patch25 PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0)
26 return 0;
31 return 0;
33 + if (invoke_psci_fn(ARM_SMCCC_VERSION, 0, 0, 0) < ARM_SMCCC_VERSION_1_1)
34 + return 0;
44 #define ARM_SMCCC_QUIRK_NONE 0
47 +#define ARM_SMCCC_VERSION 0x80000000
48 #define ARM_SMCCC_ARCH_FEATURES 0x80000001
50 +#define ARM_SMCCC_VERSION_1_0 0x10000
51 +#define ARM_SMCCC_VERSION_1_1 0x10001
[all …]
/openbmc/linux/arch/x86/include/asm/shared/
H A Dtdx.h8 #define TDX_HYPERCALL_STANDARD 0
10 #define TDX_CPUID_LEAF_ID 0x21
22 #define TDCS_CONFIG_FLAGS 0x1110000300000016
23 #define TDCS_TD_CTLS 0x1110000300000017
24 #define TDCS_NOTIFY_ENABLES 0x9100000000000010
30 #define TD_CTLS_PENDING_VE_DISABLE BIT_ULL(0)
33 #define TDVMCALL_MAP_GPA 0x10001
34 #define TDVMCALL_REPORT_FATAL_ERROR 0x10003
/openbmc/qemu/bsd-user/i386/
H A Dtarget_arch_signal.h24 #define TARGET_SZSIGCODE 0
53 #define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */
54 #define _MC_FPFMT_387 0x10001
55 #define _MC_FPFMT_XMM 0x10002
57 #define _MC_FPOWNED_NONE 0x20000 /* FP state not used */
58 #define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */
59 #define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */
/openbmc/docs/security/
H A DTLS-configuration.md230 Version: 3 (0x2)
231 Serial Number: 16242916899984461675 (0xe16a6edca3c34f6b)
246 Exponent: 65537 (0x10001)
256 cc:8b:61:6a:55:60:2b:26:55:9f:a6:0c:42:b0:47:d4:ec:e0:
265 Version: 3 (0x2)
266 Serial Number: 10150871893861973895 (0x8cdf2434b223bf87)
281 Exponent: 65537 (0x10001)
293 25:cb:5e:0a:37:fb:a1:ab:b0:c4:62:fe:51:d3:1c:1b:fb:11:
300 Version: 3 (0x2)
301 Serial Number: 10622848005881387807 (0x936beffaa586db1f)
[all …]
/openbmc/linux/drivers/gpu/drm/tests/
H A Ddrm_plane_helper_test.c20 DRM_MODE("1024x768", 0, 65000, 1024, 1048,
21 1184, 1344, 0, 768, 771, 777, 806, 0,
79 return 0; in drm_plane_helper_init()
88 KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0, in check_src_eq()
89 "src x coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
92 KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0, in check_src_eq()
93 "src y coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
122 0, params->msg); in drm_test_check_plane_state()
140 .src = { 0, 0,
143 .crtc = { 0, 0, 2048, 2048 },
[all …]
/openbmc/u-boot/board/hisilicon/hikey/
H A DREADME100 2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
135 INFO: ddr test value:0xa5a55a5a
136 INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
137 INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
138 INFO: [BDID] [fff91c18] midr: 0x410fd033
140 INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
143 INFO: acpu_dvfs_set_freq: start prof is 0x4
144 INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
146 INFO: - 0: 0x49
147 INFO: - 1: 0x49
[all …]
/openbmc/linux/tools/include/linux/
H A Darm-smccc.h18 #define ARM_SMCCC_STD_CALL _AC(0,U)
22 #define ARM_SMCCC_SMC_32 0
26 #define ARM_SMCCC_OWNER_MASK 0x3F
29 #define ARM_SMCCC_FUNC_MASK 0xFFFF
45 #define ARM_SMCCC_OWNER_ARCH 0
57 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
59 #define ARM_SMCCC_QUIRK_NONE 0
62 #define ARM_SMCCC_VERSION_1_0 0x10000
63 #define ARM_SMCCC_VERSION_1_1 0x10001
64 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-cfg-afdo.c35 .val32 = 0x20001,
41 .val32 = 0x20002,
43 /* strobe window counter 0 - reload from param 0 */
46 .offset = TRCCNTVRn(0),
51 .offset = TRCCNTRLDVRn(0),
53 .val32 = 0,
57 .offset = TRCCNTCTLRn(0),
59 .val32 = 0x10001,
77 .val32 = 0x8102,
82 .offset = TRCSEQEVRn(0),
[all …]
/openbmc/qemu/audio/
H A Drate_template.h51 for (i = 0; i < n; i++) { in NAME()
62 *osamp = 0; in NAME()
89 if (rate->ipos >= 0x10001) { in NAME()
91 rate->opos &= 0xffffffff; in NAME()
104 t = rate->opos & 0xffffffff; in NAME()
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dhfi_cmds.h12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
[all …]
/openbmc/qemu/target/arm/
H A Dkvm-consts.h26 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
30 #define CP_REG_SIZE_MASK 0x00f0000000000000ULL
31 #define CP_REG_SIZE_U32 0x0020000000000000ULL
32 #define CP_REG_SIZE_U64 0x0030000000000000ULL
33 #define CP_REG_ARM 0x4000000000000000ULL
34 #define CP_REG_ARCH_MASK 0xff00000000000000ULL
43 #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
45 #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
55 #define QEMU_PSCI_0_2_FN_BASE 0x84000000
58 #define QEMU_PSCI_0_2_64BIT 0x40000000
[all …]
/openbmc/qemu/include/hw/s390x/
H A Dsclp.h21 #define SCLP_CMD_CODE_MASK 0xffff00ff
24 #define SCLP_CMDW_READ_SCP_INFO 0x00020001
25 #define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001
26 #define SCLP_READ_STORAGE_ELEMENT_INFO 0x00040001
27 #define SCLP_ATTACH_STORAGE_ELEMENT 0x00080001
28 #define SCLP_ASSIGN_STORAGE 0x000D0001
29 #define SCLP_UNASSIGN_STORAGE 0x000C0001
30 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
31 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
32 #define SCLP_CMD_WRITE_EVENT_MASK 0x00780005
[all …]
/openbmc/linux/include/uapi/linux/
H A Ddlmconstants.h31 #define DLM_LOCK_NL 0 /* null */
46 * either return -EAGAIN from the dlm_lock call or will return 0 from
140 #define DLM_LKF_NOQUEUE 0x00000001
141 #define DLM_LKF_CANCEL 0x00000002
142 #define DLM_LKF_CONVERT 0x00000004
143 #define DLM_LKF_VALBLK 0x00000008
144 #define DLM_LKF_QUECVT 0x00000010
145 #define DLM_LKF_IVVALBLK 0x00000020
146 #define DLM_LKF_CONVDEADLK 0x00000040
147 #define DLM_LKF_PERSISTENT 0x00000080
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dxtensa.c31 int c = 0; in nvkm_xtensa_oclass_get()
47 return nvkm_gpuobj_new(object->engine->subdev.device, 0x10000, align, in nvkm_xtensa_cclass_bind()
63 u32 unk104 = nvkm_rd32(device, base + 0xd04); in nvkm_xtensa_intr()
64 u32 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
65 u32 chan = nvkm_rd32(device, base + 0xc28); in nvkm_xtensa_intr()
66 u32 unk10c = nvkm_rd32(device, base + 0xd0c); in nvkm_xtensa_intr()
68 if (intr & 0x10) in nvkm_xtensa_intr()
70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
71 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
72 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { in nvkm_xtensa_intr()
[all …]

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